Abstract: A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator for sampling the received signal in such a way that several sampling values of a bit cell transmitted with the received signal are distributed time-wise one after the other onto several output connections of the commutator device and emitted there in the form of corresponding intermediate signals. A first circuit combines a first group of intermediate signals of the commutator device into a first uniting signal, which serves as the basis for data recovery or comprises the recovered data signal, while a second circuit combines a second group of intermediate signals of the commutator device into a second uniting signal, which serves as the basis for clock recovery. The second uniting signal is fed to a phase regulator arrangement, which, dependent on this, sets the sampling phases assigned to the individual output connections of the commutator device.