Abstract: A weight operated mechanical drive consists of a cylindrical weight that is suspended by a helically threaded drive screw which passes through and engages with complementary threads within a bore defined along a rotational axis thereof. The weight turns the drive screw as it falls due to the force of gravity. The weight is prevented from rotating about the axis of the screw while it is failing by a wheel which is attached thereto and which rolls against a retaining bar that runs alongside the weight along the weight's path of travel. The retaining bar is also used to wind the weight. To do so, the retaining bar is rotated around the rotational axis of the drive screw. This action forces the weight along a path defined by the helical threads of the drive screw. The retaining bar is formed as a helix around a column through which the weight drops.

Abstract: A variable capacitor that provides a full range of capacitance, while reducing the amount of rotation necessary to effect maximum variation in capacitance, and while eliminating any wear-related deterioration in device performance includes at least two coplanar, electrically isolated sets of parallel electroconductive members so configured as to form a fixed set of capacitor plates, each of which may be separately electrically connected to an electrical circuit. A movable group having at least one member including at least one electroconductive area is positioned parallel to, and spaced from, the fixed set of plates. The movable group is adapted for rotation about an axis perpendicular to a surface plane of the first set of plates to vary an amount by which said movable group overlaps the surface of each of said capacitor plates, and thereby provide variable capacitive coupling between the two isolated electroconductive members that comprise the fixed set of capacitor plates.

Abstract: A laminated heater paddle is provided, in which a heater element having a symmetrical pattern is brazed within a heater channel defined between a first layer and a second layer. The laminated heater paddle provides brazed junctions between dissimilar metals. The heater element, having a stainless steel outer surface, is plated with nickel, and is then squeezed between the aluminum lower and upper layers. Aluminum shim stock is used between the first layer of aluminum and the second layer of aluminum or nickel plated stainless steel, wherein the aluminum shim stock provides a brazing medium. The assembly is then subjected to a vacuum, before being heated near the melting point of the aluminum. Alternative heater embodiments include guide tubes or cooling tubes between two or more brazed layers. The brazing process can alternatively be used for other applications.

Abstract: A process for producing a strip removes photoresist and extraneous deposits of polymer residue on the top surface and sidewalls of a post-metal etch wafer. The photoresist and residue are processed simultaneously by a chemical mechanism comprising reactive species derived from a microwave-excited fluorine-containing downstream gas, and a physical mechanism comprising ion bombardment that results from a radio frequency excited plasma and accompanying wafer self bias. A vacuum pump draws stripped photoresist and residues from the surface of the wafer and exhausts them from the chamber.

Abstract: A low pressure plasma ignition method and apparatus includes an ignition cylinder which passes through an anode of a vacuum chamber, where the outlet of the ignition cylinder forms a nozzle. A coil is arranged around the cylinder and a plasma-generating gas supply pipe passes through an upper part of the cylinder. A plasma-generating gas, such as Argon gas, is supplied to the ignition cylinder in this structure, such that a high density plasma is formed in the ignition cylinder that is expelled into the vacuum chamber while the pressure is reduced through the nozzle. In the vacuum chamber, the expelled plasma becomes a seed plasma, such that a low pressure plasma is readily generated in the vacuum chamber.

Abstract: A method and structure for performing data synchronization by delaying the input data for substantially one-half of the VCO signal period and then comparing the phase of the delayed input data to the VCO signal. The phase difference is filtered and controls the frequency of the VCO signal to align the VCO signal with the delayed input data. The delayed input data is clocked into a flip-flop on the opposite phase of the VCO signal to produce an output signal. In a preferred embodiment the delay of the input data for phase comparison, and the delay of the input data for the output flip-flop can be independently selected.

Abstract: An output buffer circuit advantageously uses a simple integrated circuit package including two separate ground leads for connection to an externally supplied ground voltage. The relatively large pull down current which passes through the pull down transistor of one or more output buffers are fed through a first ground lead of the lead frame to the external ground and the remaining circuitry is connected to the external ground through the second ground lead of the lead frame. The transients in the pull down current will cause ground bounce which affects the pull down transistor only, and not the remaining components of the output buffer. In this manner, base drive to the output pull down transistor is not decreased due to ground bounce, and the high to low transition of the output voltage is not degraded by the presence of ground bounce. In an alternative embodiment, the amount of ground bounce is controlled to provide a desired characteristic of the output transition.

Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Abstract: A Safe Operating Area (SOA) circuit is constructed including a synthetic large value resistor that is an active current source whose output current is related to the power supply voltage, and whose absolute value may be arbitrarily low. A piece-wise current source is provided which includes means for generating one or more control voltages in order to control the level of output current in response to the input voltage. In one embodiment, each of the control signal means includes feedback means and a summing node, so that one or more functions are performed using a control signal as an input, with the result fed back to the summing node. In this manner, a complex function can easily be provided for controlling the magnitude of the output current. In one embodiment, the one or more control signals are provided by one or more saturating current mirrors in order to limit the output current made available.

Abstract: An encryption method is taught which chooses certain bytes of data, stored in a particular on-chip memory, as encryption keys. These chosen bytes are used to encrypt themselves, and all of the remaining data in the above mentioned particular memory. The chosen bytes do not have values specifically assigned for encryption, they are merely chosen, according to a rule, from the body of data to be encrypted. When this technique is implemented, each byte of data, stored in the mentioned memory, is combined (for example using an exclusive NOR gate) with one of the designated encryption key bytes prior to disclosure. The user is not required to provide, program, or safeguard a set of key bytes separately. Additionally, no silicon area is wasted in storing such bytes. An intruder would need certain pieces of the original data in order to decipher the results of this encryption technique. Additionally, this technique degrades gracefully.

Abstract: An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure.

Abstract: A programmable logic device is constructed having a novel architecture. A plurality of control input signals are applied to a programmable mapping array in order to generate control functions for data path gating, latching, or modification. The programmable control functions provide flexibility to the designer, while the fixed data path logic is independent of the programmable array. The logic array and data path logic are fabricated on the same integrated circuit, therefore obviating the need for input/output buffers which would be necessary if the device were constructed utilizing discrete components. This enhances the performances of the device. Since the data path does not travel through the array, its performance is not affected by the programmability. If desired, the programmable array can be formed of mask programmable devices, fused programmable devices, or register based circuitry, for example, using RAM cells.

Abstract: An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure.

Abstract: An electrostatic discharge protection circuit without the use of a series resistor is described. MOSFET transistors with a turn-on voltage above the postive supply voltage but below the breakdown voltage are used. In one embodiment, parasitic bipolar transistors formed in conjunction with the MOSFETs are employed for further protection.

Abstract: A level and edge sensitive input circuit can recognize a variety of types of input signals on an input line and provide a standard digital logic output for use within the equipment. The input circuit is formed from a bias circuit, two comparators, and a memory bit. The bias circuit applies a bias voltage to the input line. A first comparator inverts the state of the memory bit when the input signals are an increment above the bias voltage. The second comparator clears the state of the memory bit when the input signals are an increment below the bias voltage. In this way, the memory bit cycles through states which provide the desired output signals for use within the equipment.

Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.

Abstract: A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.