Abstract: Disclosed is an apparatus for blanking the trailing edge of a sensed current signal taken from the leading leg of a full bridge voltage regulator. Switching elements in the arms of the full bridge voltage regulator cycle on and off in staggered phases under control of a pulse width modulation controller to provide zero voltage drop switching of the elements. With trailing edge blanking of the sensed current signal, a control waveform is generated for delivery to the pulse width modulation controller which mimics a sensed current signal taken from the lagging leg of the bridge. Such a current waveform exhibits a clear peak enhancing circuit stability thereby permitting use of leading leg current sensing to improve power supply efficiency.

Abstract: A method and apparatus for suppressing capacitive current in transformers is described. The winding of a transformer is constructed or modified into two substantially identical winding halves wired in a series aiding configuration. Two leads emanate from the center point of the winding, where the two halves are connected in series. This center point is at a constant potential throughout the switching cycle of the transformer. Suppression of the capacitive current in the input/output leads of the transformer is achieved by introducing common mode impedance into each lead and a corresponding center tap lead. The common mode impedance can be introduced in a variety of ways such as: running the pair of leads through a toroid, bead or sleeve of magnetic material; winding the leads on a magnetic toroid or rod; or using the magnetic core structure to introduce the impedance.

Abstract: The magnetic core of the transformer is an E--E shaped core. The primary winding of the transformer is divided into three substantially identical planar coils, each coil being wound on one of the three separate core posts. The coils are wired in series such that a current in the primary winding will induce substantially identical magnetic fluxes in the two outer core posts, and an opposite flux in the center post. The secondary of the transformer is formed by a contact plate and a conductor frame which provide conducting paths through the window regions of the E--E core. The bottom of the core is mounted in a recess in the conductor frame. Positioned within in the conductor frame are four rectifiers which make electrical connections to the secondary contact plate. When the transformer delivers power, the voltage on the primary winding will be divided 1/4 on each of the outer coils and 1/2 on the center coil post. During this time only two of the rectifiers will be conducting current.

Abstract: Method and apparatus for error recovery in primary storage is provided by backup storage that stores a complete copy of primary storage. When a parity error is detected, the backup storage is used to replace data in the primary storage or the parity of primary storage. This apparatus is controlled by a processor controller which makes this replacement by comparing the primary storage, backup storage, and the primary parity storage. If after re-execution of the operation errors are still detected, the processor controller copies the data from primary storage to a second storage and retries the operation.

Abstract: A semiconductor injection laser diode is coupled via a switch to two drivers. One driver provides a drive current above the threshold current required to cause the injection laser diode to lase. The other driver provides a drive current below this threshold current, causing the laser diode to operate in a light-emitting diode (LED) mode. The switch couples the laser diode to one or the other of the drivers depending upon the receiver to which the transmitter is coupled.

Abstract: A transformer with a secondary structure formed in a figure 8 pattern. The secondary structure defines two conducting paths which each incorporate a rectifier and each encircle part of the core only once. The conducting paths overlap and cross only in the window region of the core. The design of the secondary structure allows for the mechanical connections to the transformer to be physically separated on opposite ends of the transformer assembly. This structure allows for alleviation of the connector congestion and provides better cooling and also permits shorter connections to the rectifiers.

Abstract: The invention relates to methods and apparatus for isolating faults in link-connected systems utilizing fault reports generated from within the system itself. The reports are transmitted to a central location, preferably during a predetermined time period, and are used to create a single error message identifying the probable nature and location of the fault. A preferred embodiment of the invention does not require either the construction or maintenance of systemwide configuration tables, commonly used performing fault location and analysis. Instead, each unit of a pair of link coupled units, initially or on reconnection, interrogates a link adapter at the other end of the link for an identifier that identifies both the remote unit and the remote link adapter. This "nearest neighbor" information is stored locally at each unit, and is transmitted to the central location when an error is detected.

Abstract: The novel magnetic core structure of this invention provides a combination of large differential type inductance and some common mode type inductance while accommodating common mode dc current in two parallel planar conductors such as bus bars or printed circuit lands. This combination of desirable functions is accomplished by incorporating both gapped and ungapped magnetic flux paths into a single core structure. The core structure is composed of two outer posts, two inner posts, and four link segments. The two inner posts of the present core are located in the position of the center leg of a tradiational E--E core structure. Unlike a conventional E--E core, the structural arrangement of the two inner posts provides both a gapped and an ungapped magnetic flux path. The ungapped magnetic flux path travels in a figure eight pattern, encircling each of the windows of the E--E core in one of the loops of the figure eight.

Abstract: An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers in alternating fashion with frame contents bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the frame contents bytes from the selected input buffer to one of a pair of output buffers en route to the control unit. Upon detecting the receipt of the third incoming frame contents byte, the first state machine sets a start latch, causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled.

Abstract: An input/output (I/O) test and set operation is provided for testing and changing data, e.g. flags in an access status record on DASD (Direct Access Storage Device) in one atomic I/O operation, which uses a string of standard channel command words (CCW) like Read, Write, Seek and Search in combination with additional records on DASD, containing the test and set values to be used by the CCW string. The I/O test and set operation is used in a Shared Disk facility (SDF) in a flagging protocol, for avoiding simultaneous and conflicting accesses from independent computer systems having access to the same physical DASD, thus realizing a disk sharing system at user or minidisk level.

Abstract: A single-instruction-multiple-data (SIMD) array processor is described with a multi-dimensional array of processing elements and control logic for issuing global instructions to the array. Each processing element in the array has individually programmable instruction decoder and a mechanism which enables efficiently programming and reprogramming of the instruction decoder. The present invention teaches a mechanism where the processing elements may be simultaneously updated in response to a global load instruction.

Abstract: An interactive computer graphics display system processing method for identifying a displayed primitive that intersects an operator selected area of the display screen. Pursuant to the method, the operator selected area of the display screen is reverse mapped to world coordinate space; data representative of displayed geometric primitives is then clipped against the reverse mapped selected area in world coordinate space; and clipped data representative of displayed geometric primitives that intersect the reverse mapped selected area are identified for operator defined application processing. Further processing steps include mapping of the identified data to screen coordinate space and rasterization of the data for display in the screen monitor.