Abstract: The invention relates to an anti-demodulator circuit which is fundamentally built up in the same way as a demodulator circuit but, instead of a bandpass filter as generally used in a demodulator, comprises a notch filter which receives an input signal comprising a useful signal and an interference signal, and generates a filtered signal. The notch filter has a center frequency which approximately corresponds to the frequency of the input signal so as to suppress at least a part of the useful signal. The anti-demodulator circuit further comprises a mixer circuit which receives the filtered signal and a phase-shifted input signal and supplies a demodulated output signal which substantially corresponds to the interference signal.

Abstract: A data processing arrangement (1) comprises a first processor (PROC1) for providing successive sets of input data, a second processor (PROC2) for receiving successive sets of output data and a memory system (2) comprising a plurality of memory circuits (MEM) for storing the input and output data. According to the invention, the data processing arrangement further comprises a master controller (MCP) for setting up memory system by means of control commands (CC) associated with a set of input data and a set of output data. These control commands are received in the memory system by a control unit (MCU). When a data (Di) from the set of input data is provided by the first processor, this control unit selects, on the basis of the control commands, a first memory circuit and generates a write-address (AD_W) in said first memory circuit.

Abstract: A functional system comprises a set of functions (F) requiring access to a collective resource (RSRC). Such a system can be, for example, a data processing system comprising a plurality of processors requiring access to a collective memory. For reasons of cost it is desirable to guarantee a certain minimum access for one or more functions while a certain degree of flexibility as regards the access is maintained. For this purpose, the system comprises an interface (INT) adapted to implement an access scheme (AS) characterized by a plurality of states (S) passed through in a predetermined manner. A state (S) forms a possibility of access of a given length and defines an order of priority in accordance with which a function (F) can access the collective resource (RSRC).