Abstract: A comb-drive actuator includes a stationary comb structure having stationary comb fingers interdigiated with comb fingers of a mobile comb structure. The comb fingers include a p-type layer and an n-type layer forming a diode junction in each finger. The diode junctions of either the stationary comb fingers or the mobile comb finger are reversed biased, while at least one layer of the other set of comb fingers is grounded. This creates an attractive electric field between the sets of fingers, causing the mobile comb structure to move. The mobile comb structure of the actuator can be aligned along the rotational axis of a movable element and attached at one end to the movable element and at the other end to a flexure. The comb fingers can also be shaped to provide multi-gap and/or variable gap configurations between the stationary and mobile comb structures.

Abstract: A tool and method are provided for manually cutting twine wrapped around a bale. The tool includes a stem having a handle attached to one end and a hook at the other end. The hook opens reversely toward the handle. The hook includes an outer edge sharpened for cutting through ice and twine. The hook also includes an inner dull surface facing toward the handle for selectively engaging the twine upon placing the hook between the bale material and twine. The dull surface permits a user to pull the twine away from the bale without severing the twine. This allows the user to easily grasp the twine in his hand, and then cut the twine using the outer edge of the hook.

Abstract: A speech-recognition system for recognizing isolated words includes pre-processing circuitry for performing analog-to-digital conversion and cepstral analysis, and a plurality of neural networks which compute discriminant functions based on polynomial expansions. The system may be implemented using hardware, software, or any combination of hardware and software components. The speech wave-form of a spoken word is analyzed and converted into a sequence of data frames. The sequence of frames is partitioned into data blocks, and the data blocks are then broadcast to a plurality of neural networks. Using the data blocks, the neural networks compute polynomial expansions. The output of the neural networks is used to determine the identity of the spoken word. The neural networks utilize a training algorithm which does not require repetitive training and which yields a global minimum to each given set of training examples.

Abstract: A quadrant detector circuit (400) has a comparator (442) having a pair of inputs (438, 440). A first (438) of the pair of inputs (438, 440) is coupled to an in-phase signal (434) and a second (440) of the pair of inputs (438, 440) is coupled to a quadrature phase signal (436). A sample counter (448) has a reset (446) coupled to an output (444) of the comparator (442). A controllable switch (456) has a selection input (454) coupled to an output (452) of the sample counter (448). The controllable switch (456) is capable of switching between a local oscillator signal (458) and an inverse local oscillator signal (460).

Abstract: A balanced differential radio receiver (100) has an antenna (64) operative for receiving a modulated signal. A first pair of mixers (110, 112) each having an input that receives an output (106, 108) of the antenna (64) and each of the first pair of mixers (110, 112) having an output (118, 120). A second pair of mixers (114, 116) each having an input that receives an inverse output (108, 106) of the antenna (64). A resistive adding circuit (122, 124) having a pair of inputs (118, 120). The inputs (118, 120) coupled to the output of the first pair of mixers (110, 112).

Abstract: An LNS-based computer processor is provided for performing high-speed calculations that involve special function values. Special functions include transcendental and hyperbolic functions. The computer processor includes a decoder (11), a memory circuit (12) for storing a plurality of special function signals, a log converter (14), at least one processing element (16), and an inverse-log converter (18).

Abstract: Disclosed is a method for generating a high-resolution, real-time, digital video signal from an analog composite video signal such as an NTSC, PAL, or SECAM signal. The analog video signal is digitized and consecutive fields in the signal are merged to produce a frame. Non-uniform interpolation is performed between adjacent scan lines in the frame to generate the high-resolution video signal.

Abstract: A computer processor that performs operations in a logarithmic number system (LNS) domain includes a log converter (20) which generates log signals, a data pipeline (22), a plurality of processing elements (231a-f) coupled to respective stages (24a-d) of the data pipeline, an inverse-log converter (28), and a programmable accumulator (232) that performs various summing operations to produce an output signal. An instruction, selected from a set of instructions, is decoded by a control unit (234) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters.

Abstract: A handwriting recognition system achieves a higher recognition rate by using a feature extraction method which computes features based on multiple data frames. A plurality of data frames is generated from handwritten text received by the system. Each data frame includes samples taken from the handwritten text. Individual-frame features are extracted from individual data frames, and in turn, multi-frame features are extracted from individual-frame features which correspond to different data frames.

Abstract: A communications device (20) that is responsive to voice commands is provided. The communications device (20) can be a two-way radio, cellular telephone, PDA, or pager. The communications device (20) includes an interface (22) for allowing a user to access a communications channel according a control signal and a speech-recognition system (24) for producing the control signal in response to a voice command. Included in the speech recognition system (24) are a feature extractor (26) and one or more classifiers (28) utilizing polynomial discriminant functions.

Abstract: A real-time video system which performs non-uniform interpolation between adjacent vertical scan lines is presented. The video system includes a converter, a memory, an enhanced-video circuit, and a sync generator. The video system decodes and digitizes an analog composite video signal, such as an NTSC, PAL, or SECAM signal, and generates a digital video signal having a greater number of horizontal scan lines than the analog video signal. The video system is programmable to allow a different number of scan lines in the output digital video signal.

Abstract: A computing device, which may be implemented as an integrated circuit, is constructed of a microprocessor and one or more neural network co-processors. The microprocessor normally executes programs which transfer data to the neural network co-processors, which are used to compute complicated mathematical functions. Direct Memory Access (DMA) is also used to transfer data.Each neural network co-processor interfaces to the microprocessor in a manner substantially similar to that of a conventional memory device. The co-processor does not require any instructions and is configured to execute mathematical operations simply by being pre-loaded with gating functions and weight values. In addition, the co-processor executes a plurality of arithmetic operations in parallel, and the results of such operations are simply read from the co-processor.

Abstract: A method and system for storing a plurality of data blocks in a memory device is disclosed. The method stores two blocks of data elements by assign different accessing methods to the two data blocks. Three example methods of accessing the data blocks are provided by the method. The first method allows data elements of a data block to be accessed by columns in the address space, the second allows data elements to be accessed by rows in the address space, and the third allows data elements to be accessed along diagonals in the address space. The data elements may be digital words which represent exponents of a polynomial expansion.

Abstract: A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

Abstract: A neural network, which can be implemented either in hardware or software, is constructed of neurons or neuron circuits each having only one significant processing element in the form of a multiplier. The number of training examples is compared to the number of neurons in the neural network to effectuate training. The neural network utilizes a training algorithm which does not require repetitive training and which yields a global minimum to each given set of input vectors.

Abstract: An enhanced-video circuit for performing non-uniform interpolation of video scan lines is presented. The circuit includes a plurality of interpolation circuits, a memory for storing coefficients, and a control unit. The control unit is programmable to vary the scan line spacing of the output video signal.

Abstract: A processor system provides electrical power and processing to a plurality of appliances. A data bus receives a control input signal from each of the plurality of appliances and transfers electrical power and output command signals to each of the plurality of appliances. A processor, coupled to the data bus, generates an output command signal for each of the plurality of appliances in response to the input control signals.

Abstract: A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, a multiplier, and two adders. The memory stores a plurality of parameters and second-order terms which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of computing the parameters and second-order terms is also disclosed.

Abstract: In a polynomial processor a plurality of training data are received which express the desired relationship between the processor's output and input. The terms of a polynomial function are determined using a regression subsets method on the training data. The coefficient for each term is determined and the polynomial processor is programmed by loading the terms and coefficients into the processor.

Abstract: A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an inverse-logarithm converter which receives values from the processing elements, an accumulator which sums converted values from the inverse-logarithm converter, and a control unit for configuring the accumulator to perform various summing operations. The computer processor also includes a switch for providing processor outputs as feedback. An instruction, selected from a set of instructions, is decoded by the control unit to configure the computer processor to perform operations on a data stream.