Abstract: An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.

Abstract: A semiconductor device and a method of making it involve the semiconductor device (10, 71, 101, 121, 151, 201) having a substrate (11, 73, 153) with spaced source and drain regions (13-14, 76-78, 154). A gate section (21, 81-82, 123, 203) projects upwardly from between an adjacent pair of the regions, into an insulating layer (31, 83, 103, 122, 157). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (36, 87, 126), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (41-42, 91-93, 107-108, 138-139, 158) on opposite sides of and immediately adjacent the gate section. A conductive layer (51, 96, 111, 161, 171) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector structure. The emitter 36 is adjacent to and overlies the base 32 and the base 32 is adjacent to and overlies a core portion 48 of the collector structure. The collector structure includes, in addition to the core portion 48, a collector contact region 31 and a lateral collector region 50 between the core portion 48 and the collector contact region 31. The lateral collector region 50 is thinner than said collector contact region at some point along its length.

Abstract: A system for determining a position error in a wafer handling device includes a control module, an image acquisition module, and an image analysis module. The control module moves a workpiece having one or more reference marks, and the image acquisition module captures an image of at least one reference mark. The image analysis module, which is coupled to the image acquisition module, compares the captured image to stored target information to determine a position error.

Abstract: A method for determining contact coplanarity of packaged semiconductor devices having a plurality of contacts. The method includes the steps of measuring the relative positions of the contacts on a subject semiconductor device; calculating from the measurements seating planes 64 formed by tilting the device to one or more of its corners and/or sides such that each said plane comprises contacts at or adjacent to the corners of the device; using the measured relative contact positions and the calculated seating planes to determine the highest deviation from contact coplanarity for the semiconductor device.

Abstract: The invention relates to an LOC type semiconductor device having improved heat radiation. The semiconductor device related to the present invention has a preferably metal heat-radiating element 7 that is in thermal contact with the surface opposite the principal surface of the semiconductor chip 3. One region of said heat-radiating element 7 is externally exposed from the package that encloses the semiconductor chip 3. The heat-radiating element 7 is in thermal contact with a metal pattern 12 that is formed on the substrate 10 on which the semiconductor device is mounted. The heat from the semiconductor chip is transferred to the mounting substrate 10 side via the heat-radiating plate 7, and heat dissipation is conducted efficiently.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.

Abstract: A system (10) and method (30) for precisely depositing a solder compound onto a substrate (18). The system (10) generally includes a receiving member (20) having a rotatable portion (21) adapted to receive a planar substrate (18), a horizontal member (12) for depositing solder balls (11) on the substrate (18), and a contact member (14), located between the receiving member (20) and horizontal member (12). The contact member comprises an aligner plate (14) having a pair of stoppers (15) protruding therefrom. Advantageously, pivotable portion (21) of the system (10) establishes the planarity of the substrate (18), with respect to the horizontal mount (12) allowing for the solder balls (11) to be mounted thereon, preventing the substrate (18) from being slightly misaligned, warped, and/or tilted.

Abstract: A heat dissipating flip-chip Ball Grid Array (BGA) (10) including a substrate (12), a die (14), a first set of solder balls (16) coupling the die with the substrate, a thermal compound (20) attached to a backside of the die, a second set of solder balls (28) attached to the substrate, and a printed circuit board (22) that includes a heat dissipating metal (24). The heat dissipating metal is in contact with the thermal compound, and the second set of solder balls is connected to thermal vias in the printed circuit board.

Abstract: A work station for a chip bonder, and/or for a wire bonder includes a clampless, porous ceramic vacuum chuck where the substrate under assembly is securely and uniformly held by vacuum applied through many tiny pores distributed across the work surface. Porous ceramic work stations are applicable to a family of packages, or to a substrate outline, and may include one or more chips within the same indexing operation. Reliability and yield of the assembled semiconductor devices is enhanced by avoiding uneven or warped substrates. In addition, the porous ceramic work holder provides a cost effective apparatus by eliminating device specific clamps and work holders, the time required for change-out and set-up.

Abstract: A photolithography system includes a photolithography tool 32 that includes a stage upon which a semiconductor wafer is mounted. The tool is operable to move the stage to automatically focus a pre-determined image on a surface of the semiconductor wafer. The tool is further operable to log movements of the stage. The system also includes an automation host computer 36 operable to poll the photolithography tool 32 to obtain data reflecting the logged movements of the stage. The automation host computer 36 is further operable to analyze the data and compare the data to pre-determined error conditions. The host computer also takes a pre-determined action, including sending an electronic mail message to the personal computers 38 of relevant line personnel, in the event the data meets the pre-determined error conditions.

Abstract: An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.

Abstract: A system for simultaneously securing a plurality of integrated circuits in a test fixture, comprising a base supporting a test board having a plurality of sockets. Each socket is configured to receive a integrated circuit and has a locked position and an unlocked position. The system further comprises a fixture adjacent to the test board and plurality of sockets comprising a support mechanism connected to the base, a contact region coupled to the support mechanism, and a means for moving the contact region to a contact position whereby the contact region, when in the contact position, contacts the plurality of sockets to move the plurality of sockets to the unlocked position.

Abstract: A computerized system and method for reducing bond program errors in a slave bonder, prepared to attach connecting bonds onto bond pads of a slave integrated circuit, by first collecting, on a master bonder, input data concerning bond x-y locations, alignment reference x-y locations, and alignment reference images from a master integrated circuit, then analyzing these data to construct a network of relationships between reference images and bond locations, and store data and relationships in a master file. Secondly, on a slave bonder, all this information is automatically retrieved and compared by a computer with input data concerning alignment reference images from a slave circuit. Thirdly, any discrepancy found is corrected by a computer to identify the new bond locations on the slave circuit. Finally, the slave bonder attaches the connecting bonds based on the computed correct bond locations.

Abstract: A testing system for testing an integrated circuit device includes a test definition generator program which generates an initial test definition from information that includes test data. A checker program checks the initial test definition for compatibility with each of at least two different testers. Each of the testers includes a hardware interface, native software having driver routines for the associated hardware interface, and a compiler compatible with the driver routines. Each tester includes a converter program which has been compiled by a compiler other than the native compiler, and which converts the initial test definition into a modified test definition. The modified test definition is interpreted by an interpreter program, which has been compiled by the native compiler, and which controls the hardware interface through the native driver routines so as to carry out the test definition.

Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.

Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.

Abstract: An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers include a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip.