Abstract: The invention is embodied in an optical memory having a holographic recording medium capable of storing respective holograms in respective storage spots, the memory including a coherent collimated reference beam and an information-bearing object beam illuminating the recording medium, a segmented optical array including a stack of plural segmented optical sub-arrays, each of the segmented optical sub-arrays including an array of generally parallel optical strips, each optical strip having a strip length extending parallel to the optical strips, respective optical strips of all of the sub-arrays providing an optical path for the reference beam to respective recording spots in the holographic recording medium whenever the reference beam is incident within the strip length, two optical strips in different sub-arrays with optical paths to the same recording spot being separated by at least an out-of-plane multiplexing difference angle subtended by paths of the reference beam to the two optical strips, a reference

Abstract: The invention is a fiber-optic communication network, including a fiber-optic coupler having multiple fiber-optic ports and multiple optical transceivers which are individually connected to one of the fiber-optic pods. Each optical transceivers includes apparatus for transmitting to and receiving from the fiber-optic coupler, optical pulse signals in accordance with a predetermined code sequence of the transceiver, and optical amplifiers for amplifying the optical pulse signals. Each optical transceivers also includes apparatus for spectrally phase encoding/decoding, in accordance with the predetermined code sequence, optical pulse signals being transmitted to and received from its associated fiber-optic port, and apparatus for reconfiguring the code sequence in accordance with a user select signal. Each optical transceivers further includes detection apparatus for detecting a received optical pulse signal transmitted from another of the optical transceivers.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array.