Abstract: A method, computer program product, and data processing system for facilitating the traversal of a hierarchy of GUI components containing components and/or containers from disparate GUI toolkits is disclosed. In a preferred embodiment, auxiliary associative data structures relating parent components in one toolkit to children in another toolkit are defined. When examining a component to determine if it has children, an appropriate associative data structure is consulted to determine if that component has a child from a disparate toolkit. In accordance with this preferred embodiment, additional associative data structures are defined, which also record the reverse “child-parent” relationship, so as to allow the GUI component tree to be traversed in both directions.

Abstract: A method, computer program product, and data processing system for detecting and identifying data crossover errors in servlet code are disclosed. According to a preferred embodiment, techniques of aspect-oriented programming (AOP) are used to instrument JAVA Servlet code to detect potential data crossover errors. Specifically, pointcuts are defined to intercept both the association follow an object with a particular session and the “getting” and “setting” of such objects. Advice code associated with these pointcuts is used to update and/or consult a “collator” data structure, which is used to determine if an object or variable associated with one session is being accessed by a different session. In a preferred embodiment, the AspectJ aspect-oriented programming language/system is used to define the pointcuts and advice code.

Abstract: A method, a computer program product and a system for reconfiguring functional capabilities in a data processing system with dormant resources. Dormant resources of a data processing system are used to replace (360) the functional characteristics of a broken hardware unit in order to compensate the lost resources. If sufficient dormant resources are available to replace the functional capabilities of the broken hardware unit, the data processing system can be used without any degradation of its capabilities. Otherwise the degradation is reduced. The functional part of the broken hardware unit is fenced (340) from the system, but its configuration data is read (350) from its non-functional part. The enablement definition data contained in the configuration data is then analysed for missing resources. Available dormant resources are then enabled until all the lost resources are replaced or no more dormant resources are available for the replacement.

Abstract: A method and system whereby new devices may be introduced for use with a particular device driver without necessitating a change to the device driver binary is disclosed. In a preferred embodiment of the present invention, an option ROM is provided within the hardware device. Program code contained in the option ROM executes during the system boot process and reads the vendor ID, device ID, subsystem vendor ID, and subsystem device ID from the device. This option ROM code then determines, based on the vendor ID, device ID, subsystem vendor ID, and subsystem device ID, whether to write a signature to a scratch pad register of the device. When the operating system is booted, the driver reads the signature written by the option ROM code. If the signature matches the signature programmed into the driver, the driver claims the device as its own and continues to load.

Abstract: An access (utilization) controller to restrict or block visual or aural interaction between a vehicle operator/driver and mobile communications and information devices such as computers, mobile telephones, pagers, personal digital assistants (PDAs), and the like mounted on or used in the vehicle is disclosed. The utilization controller comprises sensors to detect motion or “potential” motion of the vehicle, a processor receiving data from the sensors and inhibitor means responsive to the processor to “blank out” or otherwise inhibit any distracting visual or aural output from the communications or information devices while the vehicle is in motion or about to move. The sensor data such as speedometer, transmission gear position indicator, antilock brakes and others are extracted from a vehicle's internal monitoring and control systems.

Abstract: A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage.

Abstract: An apparatus, computer program product, and method for preventing piracy in combined hardware/software products, and specifically in RAID storage systems is disclosed. In a preferred embodiment of the present invention, when a hardware device (a disk controller, in a preferred embodiment) is initialized, the device executes firmware that directs it to write a signature to a storage location (scratchpad register) in the device, where the signature corresponds to a set of product features authorized for use with the hardware device. When application code executing on the host computer system attempts to access a feature (e.g., through device driver code), the stored signature is read from the hardware device. The code implementing the feature is allowed to execute only if the signature that is read from the hardware device matches a feature level of the product in which that feature is authorized.

Abstract: A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced (51) by pseudo inputs. The input signal values of the multiplier circuit are determined (54) automatically from a counterexample (53) delivered (52) by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined (55) with other known inputs to form a test case (56) file that can be used by a logic simulator to analyse the counterexample (52) on the unmodified hardware design including the multiplier.

Abstract: Disclosed is a controller to prevent access or utilization by a vehicle operator to communications devices installed on the vehicle when the vehicle is in motion thereby reducing distractions of the operator.

Abstract: A quilting frame apparatus is disclosed, which provides a user with a more efficient work area than is provided with traditional quilting frames. The quilting frame apparatus comprises concentric rectangular outer and inner frames. The outer frame is constructed from four elongate members attached in a mortise-and-tenon arrangement at each of its four corners and secured by wingnuts. The quilting frame may be adjusted at different angles to suit the user. The apparatus may also be folded for convenient storage.

Abstract: A method, processor architecture, computer program product, and data processing system for determining when an instruction in a pipelined processor should be completed is provided. As each instruction is issued to an execution unit, an entry for that instruction is placed within a “finish pipe,” which consists of a series of consecutively numbered stages. Each clock cycle, the entries in the finish pipe advance one stage. When an entry has reached the stage corresponding to the latency of its associated execution unit, it becomes mature. Each clock cycle, the finish pipe is scanned to find the entry having the highest-numbered stage of any entry in the finish pipe. If that entry is mature, it is removed from the finish pipe and the instructions associated with that entry is allowed to complete. If not, the entry simply advances along with the other entries and the pipe rescanned in the next cycle.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols.

Abstract: A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the host. The Host Channel Adapters are registered with the memory region so that each adapter stores an address pointer to the tables. In this way, the tables need not be duplicated for each adapter.

Abstract: A method of de-allocating multiple processor cores sharing a failing bank of memory is disclosed. The method allows new multiple-processor integrated circuits with on-chip shared memory to be de-allocated using existing technology designed for use with single-processor integrated circuit technology.

Abstract: The value of non-discrete metric variables are synchronized at the processor level. When the profiler requests metric information for non-discrete metric variables, the operating system kernel obtains a global value for the requested metric rather than obtaining per-processor metric values for each processor. The global value may be written to trace records. By using a single global per-processor metric for all processors, a single global value of the last metric variable may be used for calculating the resources consumed on all processors since a last recorded event.

Abstract: A program is profiled with enablement of trace record generation during a first period of time and with disablement of trace record generation during a second period of time. The number of trace records output during the first period of time is determined, and a trace overhead calibration value is computed as an average time for writing the number of trace records output during the first period of time. The trace overhead calibration value may be stored for subsequent use in a profiling-related process in the data processing system. The trace overhead compensation value represents the amount of time required to generate a trace record, and the trace times retrieved from the trace records are adjusted to compensate for the amount of time required to generate those trace records.

Abstract: A computing system including a plurality of data processing systems and a peripheral input device. The peripheral input device includes a computer selector for selecting one of the plurality of data processing systems for interaction with the peripheral input device. The peripheral input device also includes a wireless transmitter for providing communications with any one of the plurality of data processing systems. Each of the plurality of data processing systems includes a wireless receiver for receiving wireless communications from the peripheral input device.

Abstract: A method and system for monitoring performance of a program is provided. A trace record containing a call stack associated with the program is periodically generated. An occurrence of a selected event or a timer interrupt is detected, and in response, an execution context sample is obtained that contains a process identifier, a thread identifier, a program counter, and a stack pointer. A trace record containing the execution context sample data is generated. During post-processing, the execution context samples are compared with a call stack to identify the routine associated with the execution sample data.

Abstract: A method and apparatus for a process in a computer for processing a method that performs a function. A determination is made as to whether the method is to be executed normally when the method is loaded. Responsive to an absence of a determination that the method is a method to be executed normally, instructions native to the computer are associated with the method, wherein the instructions perform the function.