Abstract: A way prediction scheme for a partitioned cache is based on the contents of instructions that use indirect addressing to access data items in memory. The contents of indirect-address instructions are directly available for use, without a memory address computation, and a prediction scheme based on this directly available information is particularly well suited for a pipeline architecture. Indirect addressing instructions also provide a higher-level abstraction of memory accesses, and are likely to be more indicative of relationships among data items, as compared to the absolute address of the data items. In a preferred embodiment, the base register that is contained in the indirect address instruction provides an index to a way-prediction table for an n-way associative cache.
Type:
Grant
Filed:
March 13, 2001
Date of Patent:
November 4, 2003
Assignee:
Koninklijke Philips Electronics N.V.
Inventors:
Jan-Willem Van De Waerdt, Paul Stravers