Abstract: Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.

Abstract: A method and apparatus for a pre-biasing storage mechanism to prevent oxidation and other contaminants from forming on the probe tips and probe tails of a probe card. The pre-biasing storage mechanism imposes a positive bias on the probe needles of the probe card so as to create physical contact between the probe tails and the conductive pads of the printed circuit board (PCB) arrangement of the probe card during a disengaged state of the probe card. In addition, the storage mechanism imposes a positive bias on the probe needles of the probe card, so as to create physical contact between the probe tips and a probe tip cleaning pad, or other protective surface, during a disengaged state of the probe card.

Abstract: A method is provided whereby a placement-based cost function is utilized to minimize leakage and dynamic power that is consumed by clock networks implemented within integrated circuits (ICs) such as field programmable gate arrays (FPGAs). An initial placement of clock signal loads is analyzed to determine whether an alternative placement of clock signal loads results in the reduction of the usage of vertical clock spines, or equivalently, the optimization of the cost function. Several desirable characteristics are obtained through strategic clock signal load placement within the FPGA in accordance with the cost function. First, the number of clock regions spanned by a particular clock signal is minimized. Second, interconnect capacitance within the clock region is also minimized. By minimizing the total capacitance of a particular clock network implemented within a clock region, the leakage and dynamic power consumed by the clock network within the clock region is also minimized.

Abstract: A method and apparatus for an adaptive systolic array structure is initially configured for motion estimation calculations and optionally reconfigured as the motion estimation algorithm progresses. A scheduling map of the processing element (PE) calculations for a given motion estimation algorithm is generated. A systolic array structure may then be generated from the scheduling map, whereby the size and shape of a processing element array is configured to generate the search pattern that is to be used during the search. In addition, delay elements may be implemented within the systolic array structure, so as to preserve the pixels of a current macroblock that are reused in accordance with the scheduling map. The systolic array structure may also be adapted by the motion estimation algorithm during subsequent search stages to accommodate refinements required by the search strategy.

Abstract: A method and apparatus is provided for the calculation of maverick control limits. The maverick control limit method selects the correct parameter(s) as critical parameters to be utilized by the maverick control limit method. Next, the maverick control limit method identifies the probability density function that is associated with the parametric data set(s) that are associated with the critical parameter(s). Next, abnormal data points within the measured parametric data set(s) are removed. Maverick control limits are then calculated to properly disposition semiconductor die into pass/fail categories.

Abstract: An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

Abstract: A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device is disclosed. The semiconductor device includes a gate stack having first and second sidewall spacers, where the gate stack is implemented above the channel region of the semiconductor device. The semiconductor device further includes first and second trenches formed adjacent to the gate stack, where the first and second trenches are conically shaped to be wider at a top portion of each trench as compared to a width of each trench below the top portion of each trench. The semiconductor device further includes strained silicon alloy formed within the first and second trenches, where a stress force exerted on the channel region of the semiconductor device is maximized at a surface of the semiconductor device below the gate stack.

Abstract: A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check stop facilitates a snap shot of the hardware and/or software state of the IC to be stored into hardware and/or software based memory. Should a soft error be detected, execution is halted and the executable state of the IC that conforms to a previous check-stop location may be re-established after the soft error(s) are optionally corrected. In alternate embodiments, hardware based mechanisms may be exclusively utilized to both detect and correct the soft errors.

Abstract: An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a phase locked loop (PLL). The frequency difference is then used to adjust the local oscillator's frequency to be changed by a value that is proportional to the frequency difference measured. Through adaptive calibration of the local oscillator's frequency prior to closed loop PLL operations, a substantial reduction in the amount of time required to obtain phase/frequency coherent operation of the PLL is realized.

Abstract: A method and apparatus is provided for the automatic creation of timing constraints that are based upon input interface timing parameters entered through a graphical user interface that is associated with the one or more input interfaces. Ideal timing constraints are created from the input interface timing parameters for the one or more input interfaces, thereby enabling the analysis of the input interface(s) without requiring explicit constraints to be defined by the designer of the input interface(s). Timing constraints may, therefore, be automatically generated by the designer without the need for the designer to possess any detailed knowledge of the associated constraint language parameters. Once created, the automatically generated timing constraints are graphically displayed to the designer for verification and/or modification. The automated process removes any potential for improperly defining the input constraint language parameters associated with the input interface(s).

Abstract: A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affected by the electrical disturbances. Next, principles of superposition are utilized to coherently combine each of the electrical disturbance waveforms in the time domain to generate the predicted SSO noise waveform that is imposed upon the affected signal conduction path. The electrical disturbance waveforms may be produced either by using bench measurements performed on an actual integrated circuit, by simulation, or by a combination of simulation and bench measurements.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: A method is provided to incorporate information currently known about an integrated circuit's design, including peripheral components that share the same printed circuit board (PCB) with the integrated circuit, to automate a clock signal instantiation and routing solution to realize a comprehensive design. The information derived from a hardware design synthesis tool includes the existence of PCB resources, such as fixed-frequency oscillators, that may co-exist with a particular integrated circuit, such as a programmable logic device (PLD). Other derived information includes details concerning clock modules and cores that may exist within the PLD in accordance with the PLD's design specification.

Abstract: A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.

Abstract: A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the timing information, or conversely, propagated by request via a training sequence. All system components other than the master system component do not require a separate clock input, since frequency coherency is maintained by internal time bases that have been calibrated to the frequency of the propagated timing information.

Abstract: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Abstract: A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE) in a unified signaling system. An input data stream is sliced into an even data stream and an odd data stream, whereby the sliced data is compared to a programmable threshold depending upon a detection mode. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, a correct portion of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is summed in current mode with the feedback data and converted to voltage prior to sampling the currently received data bit.

Abstract: Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.

Abstract: A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity PSV generator, such that the need for multiplication operations is obviated. Each evaluation cycle performed by the reduced complexity PSV generator is modified by each primitive root of the desired discrete power series. For each PSV generated, a corresponding address is calculated to indicate the correct placement of the PSV generated.

Abstract: An apparatus and method of utilizing an electron beam and ion beam microscope in combination with nanomanipulators to improve the accuracy of the characterization of structures within an integrated circuit. Probes attached to the nanomanipulators, i.e., nano-probes, are applied to the features of interest via a first trench, while physical dimensions of the features of interest are altered via a second trench. As such, the nano-probes may remain attached to the feature being characterized, while alteration of the feature is conducted from the second trench to obtain 3-dimensional characterization of the feature of interest with improved accuracy. The nano-probes may also be used to apply the test stimulus to the features of interest, or conversely, an electron beam microscope may be used.