Abstract: An optocoupler package made up from a pre-assembled package having a leadframe, a voltage isolation barrier, and a body molded from a reflective plastic material. The voltage isolation barrier is fabricated as part of the body and positioned in such a way as to substantially increase the electrical flashover path between the optical source and the optical detector. An optical source mounted in the pre-assembled package subsequent to fabrication of the molded body. An optical detector is optically coupled to the optical source by reflection within the pre-assembled package, the optical detector being mounted in the pre-assembled package subsequent to fabrication of the molded body A reflective plastic cover is bonded to the pre-assembled package.

Abstract: An environmental chamber for a transmission electron microscope, in which a specimen is held in position within the transmission electron microscope so an electron beam passes through the specimen to a detector. A removable sleeve surrounds the specimen holder and is sealed at both ends by a seal between the removable sleeve and the specimen holder to form a differential pressure chamber. Apertures are formed in the removable sleeve allowing the electron beam to pass through the specimen to the detector. A vacuum line allows gases to be removed from the differential chamber. A reactive inlet line extends into the differential chamber to allow a material to be introduced onto the specimen.

Abstract: A superluminescent surface light emitting device comprising a mirror layer (19) formed on a surface of a semiconductor substrate (22). Above the mirror (19) is a light emitting region (16). A second mirror (12) is located in a plane above the light emitting region (16). The combined reflectivities of the mirrors (19,12) are selected such that light is emitted in the superluminescent operating mode in a direction perpendicular to the surface of the device. An implanted region (14) may be used to improve superluminescent operation.

Abstract: Optimization of test stimulus verification by analyzing test stimulus timing information against restriction rules derived from a static analysis of a digital system. The result of this analysis is used to determine test stimulus timing which cannot cause a timing violation and to remove the associated vectors from further checking. Only those vectors which can violate timing constraint rules are checked individually to find states which violate the timing rules.

Abstract: A memory structure and related method for collecting and maintaining data descriptive of a multiplicity of interrelated process flows is disclosed. A complex memory structure includes job entities, operation entities, and process entities. Operation entities are subordinate to job entities, and process entities are subordinate to operation entities. These entities are represented by tables which are linked together to indicate their position in the hierarchy and their sequencing within a process flow. The process entities describe specific activities accomplished by an organization in achieving organizational goals. Typically, resources are either consumed or released, or both, during a process. Bill-of-resource tables are subordinate to process entities and populated with data which identify resources consumed by corresponding processes in the process flow.

Abstract: A portable interprocess communication facility by which different processes running simultaneously on a network of computer systems can efficiently communicate variable sized data blocks between each other. This involves the elements and techniques necessary to achieve high speed communication, without requiring the processes to be located on the same physical system or to be completely dependant upon the particular design or revision of the operating system in which they run. In addition, the invention simplifies the task of porting a modular software system between different hardware devices and operating systems by allowing communicating processes to be only loosely connected to the operating system.

Abstract: A rule based floorplanner for a macrocell array having a plurality of predetermined macrocells. The floorplanner uses a net list (23), a macrocell list (26), and a list of design constraints (31) and characteristics of the base array itself to derive an initial Burain score. A trial floorplan is attempted (33) and checked against a list of theoretical rules (39) and a list of empirical rules (38) to determine a measured Burain score (36) which accurately indicates the difficulty which can be expected when completing the design.

Abstract: An apparatus which efficiently coordinates the association of resource and lot data in a manufacturing environment is disclosed. The apparatus includes a memory structure which associates resource and lot data only with other resource and lot data from a common dependency. A dependency is a characteristic of lots which share common resources and of resources which are shared by common lots. The memory includes nodes which describe the dependencies. The dependency nodes link to resource lists and to lot lists. The resource and lot nodes are part of resource and lot lists, respectively. Usage nodes are included to describe every use each lot makes of each resource. The usage nodes are linked to both resource nodes and lot nodes. The usage nodes are also linked together to define the order in which each lot uses its resources and the order in which each resource is used by its lots.

Abstract: A circuit for a boundary-scan cell for the JTAG Architecture, the circuit including a capture section(50) coupled in cascade to an update section(52),and each section comprising a flip-flop (34,36)having a clock input for receiving a common clock signal (TCK, TCKB) and a multiplexer having a first input for receiving an input data signal, a second input coupled to an output of the flip-flop, an output coupled to a flip-flop input, and a select input for receiving a control signal for selectively coupling the first or second input to the multiplexer output.

Abstract: A plastic package (10) with a heat sink (11, 27, 28, 32) has a stress relief wall (18, 21, 33) formed on its upper surface. A semiconductor die (12) is mounted on the heat sink (11, 27, 28, 32) such that the top of a semiconductor die (12) is below the level of the top of the wall (18, 21, 33), and the wall (18, 21, 33) absorbs stresses which otherwise would be applied to the semiconductor die (12). The package (10) is simple to fabricate and assemble, and provides a mold lock (23, 24, 31) which serves to hold the plastic material (13) tightly to the heat sink (11, 27, 28, 32). Extra die bond material (26) can be used to increase heat flow without compromising other characteristics of the package (10).

Abstract: A current source with adjustable temperature compensation in which the level of current supplied to a load is adjusted to compensate for the load's inherent change in performance with changes in temperature. The current source allows selection of the appropriate temperature compensating characteristic and operating current solely by altering internal component values.