Abstract: A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter.

Abstract: A printed circuit board is provided having one or more lands formed upon the outer surface of the printed circuit board. Each land is adapted to receive a surface mount component and, specifically, leads extending from the surface mount component. Each land is fabricated having an inwardly facing exposed surface which, when the lead is placed upon the land, directs or channels the lead toward the center of the land to enhance interconnect accuracy of the lead to the land. Moreover, various configurations of solder are placed upon the land, wherein the solder can be deposited at select regions on the land or at a controlled thickness. Careful placement of solder helps ensure the lead, once placed, will not migrate or misalign from the land during subsequent reflow. Careful placement of solder helps minimize surface tension imbalance of the molten solder by assuring surface migration in a controlled direction to the middle of the land.

Abstract: Using a thermal/vacuum forming process a thin film polymer substrate is shaped into a generally shroud-like EMI shield body which forms a portion of a multi-layer EMI shield structure removably secured to a side of a printed circuit board disposed within a plastic computer housing, over operating components disposed on the circuit board. An inner side of the polymer substrate body, which faces the operating components, has a metallic conductive layer formed thereon which, in turn, is covered by a layer of insulative material. During the application of the insulative material to the conductive layer, spaced, coplanar attachment portions of the metal clad shield body are masked on their inner sides so that in the finished EMI shield structure the conductive material on these attachment portions is exposed.

Abstract: A system for connecting a plurality of input/output (I/O) channels to a single computer system bus. A system controller establishes priority among the I/O channels competing for access to the system bus. A plurality of I/O channel bridges are connected to the system bus and interface with EISA channels. The I/O bridges receive data from the EISA channels at one data rate and transmit the data to the system bus at another data rate. Data is stored within the I/O bridges in a cache memory device until commanded to transmit the data to the system bus by the system controller.

Abstract: A watchdog timer circuit of the present invention monitors a computer system (S) during diagnostic testing and resets the system when it is nonfunctioning. A real-time clock (RTC) (21), programmed by a central processing unit (CPU) (29) to run for a period of time, produces a reset signal after the period of time elapses. Typically this time period relates to a diagnostic program being run. The reset signal serves as an input to reset circuitry (28) which immediately transmits a nonmaskable interrupt (NMI) to the CPU (29) and, after a delay period, transmits a hardware reset signal to the CPU (29). When functioning properly, the CPU (29) prepares for the hardware reset signal that is produced by the reset circuitry (28) and avoids being reset by the hardware reset signal. However, when the CPU (29) is not functioning properly, the hardware reset signal resets the CPU (29).

Abstract: Disclosed are a configuration-dependent video memory clock selection circuit and method for a computer system. The selection circuit operates in conjunction with a removable video memory module. The module comprises: (1) a circuit board capable of insertion into the computer system as a daughter-card, (2) a plurality of video memory chips located on the circuit board and having a particular logical configuration and (3) a configuration indication circuit located on the circuit board, the indication circuit capable of providing a configuration signal representing the particular logical configuration to video clock signal generator circuitry in the computer system when the circuit board is inserted into the computer system. Thus, the configuration indication circuit and the video clock signal generator circuitry act in concert to provide a configuration-dependent video memory clock selection circuit.

Abstract: A portable computer has a base housing portion to which a display screen structure is pivotally connected. The display screen structure is defined by a solid, relatively thin plastic screen panel instead of the usual lid/display screen housing having mounted therein an LCD panel, a panel illumination system and associated display electronics. To form a selectively variable image on the screen panel a relatively small LCD projection structure is mounted on the top side of the base housing for pivotal movement relative thereto between an upwardly extending use orientation and a downwardly retracted storage and transport orientation. The LCD projection structure includes a lens housing having a lens disposed therein, a small LCD projection panel supported on an underside portion of the lens, and a high intensity light source supported beneath the LCD projection panel.

Abstract: A method for configuring at least one composite drive for a disk drive array controller. A disk drive array controller having a memory portion on which a list of composite drives which may be installed on a bus of a computer system is stored thereon is provided. A plurality of disk drives are then installed on the bus of the computer system. Each of the disk drives includes a user data region, a first portion of which contains a first field containing a composite drive ID number for a composite drive and a second field which indicates the total number of disk drives in the composite drive corresponding to the composite drive ID number and a second portion of which contains a position of the disk drive within the composite drive corresponding to the composite drive ID number.

Abstract: Disclosed are a circuit and method for dynamically determining cache memory size. The method comprises the steps of (1) writing a replacement data pattern into a first addressable location of a cacheable portion of addressable space, thereby placing the replacement data pattern into a corresponding first addressable location in a cache memory and setting a tag in the first addressable location, (2) accessing an assumed number of remaining addressable locations in the portion of the addressable space thereby setting tags in each of the remaining addressable locations and (3) reading the first addressable location in the cache memory to determine whether the replacement data pattern remains in the first addressable location, the cache memory being of an assumed size if the replacement data pattern is not in the first addressable location in the cache memory. The circuit and method are able to size cache memory without reference to cache size data stored in cache controllers or hardware timers.

Abstract: A disk controller which minimizes the rad operations required during parity writes of less than a single stripe. The disk array can be generalized as including N+1 disk drives with each stripe including a block on each of the N drives storing data and a block in 1 drive storing parity information. The present invention operates during writes to K blocks of a stripe where K is less than N, i.e., a partial stripe write. If K is greater than (N-1)/2, the N-K unwritten blocks are read in order to compute the new parity information before the actual write take place. If K is less than or equal to (N-1)/2, then the controller only reads the old parity information and the old data in the sectors to be written to compute the new parity. Thus the number of reads required to compute the new parity information is minimized.

Abstract: A system for controlling the operation of computer power and reset switches. A separate key switch enables a user to selectively disable the power and reset switches of the computer. The user has the option of operating the computer in a secured mode, in which a user key is required to actuate the power and reset switches, or alternatively in an unsecured mode in which the power and reset switches operate normally. Control circuitry is connected to the switches and operates in the unsecured mode for enabling power supply and reset circuitry operating state transitions responsive to the user actuation of the respective switches. In the secured mode, the circuitry disables the power supply state transitions that normally would occur responsive to user actuation of the first switch, and disables the reset circuitry state transitions, but only from the inactive operating state to the active operating state, so the reset circuitry is prevented from remaining in a continuous reset loop.

Abstract: Disclosed are an apparatus and method preferably for testing personal computer (PC) bus transmission line characteristics. The apparatus comprises: (1) a plurality of transmission line segments having different physical dimensions, each of the plurality of segments having a different electrical effect on signals transmitted thereon and (2) a switching circuit capable of coupling successive ones of the plurality of segments to an external conductor, an electrical characteristic of the external conductor affected by the coupling of the successive ones of the plurality of segments thereto, the apparatus permitting signals to pass through the external conductor and a selected one of the plurality of segments via the switching circuit. The apparatus allows a determination of a susceptibility of the external conductor to changes in transmission line electrical characteristics brought about by various possible combinations of peripheral expansion bus cards.

Abstract: Apparatus and method is disclosed for removing an integrated circuit chip from a socket in a printed circuit board without damaging the chip or other components on the circuit board. The tool has a pair of arms slidably attached to a base. The lower ends of each arm have wedge-shaped teeth projecting inwardly toward the base. Components are provided within a cavity in the base for evenly and simultaneously moving the arms and teeth inwardly toward the base. The wedge-shaped teeth are thereby driven between the socket and chip so that the chip is forced away from the socket by the inclined upper surfaces of the teeth until the chip is disengaged from the socket. The even action of the teeth disengages the chip from the socket without bending pins of the chip or otherwise damaging the chip. Further, the tool does not rest upon or press against the circuit board as the chip is removed from the socket, so the tool removes the chip from the socket without damaging other components on the circuit board.

Abstract: A hand-held keyboard test unit includes an enclosure that fits easily within one hand, a keyboard connector for receiving a keyboard connector, a controller programmed solely to execute tests of the keyboard, a digital display to indicate the status of the test and provide instructions to the test unit operator, and a switch to initiate the test sequence. The controller causes the keyboard to execute its self-test routines, transmits and verifies responses to standard system unit commands to the keyboard, and conducts a key closure test for each key on the keyboard.

Abstract: Transverse electromagnetic mode (TEM) radiation emitted from a side edge portion of a circuit board substrate portion during operation of the circuit board is intercepted by a specially designed shield structure carried by the substrate side edge portion, and the intercepted radiation is conductively returned to the substrate ground plane, through a relatively short grounding path, for return to the emitting source(s). In one form thereof, the shield is a copper plating material extending along and covering the substrate side edge portion and adjacent peripheral portions of the opposite sides of the substrate. In another form thereof, the shield is a snap-on metal shield structure that is removably mounted around the substrate side edge portion. The shield may be electrically coupled to the substrate ground plane by directly contacting a ground plane edge portion with the copper plating, using a filter structure to couple the shield to the ground plane, or otherwise using an external grounding path.

Abstract: A disk drive array including a controller which provides scatter/scatter (bi-directional scatter/gather) operations between noncontiguous host memory address locations and noncontiguous disk address locations. The host provides a single request to launch a scatter/scatter transfer. The single data request includes a pointer to a list of transfer counts and addresses, the length of the list, and the starting logical address on the disk transfer. Skipped blocks in a scatter/scatter request are specified by data address value of -1, and a no-operation (no-op) request is enqueued for each skipped block. Thus, during reads the controller extends the scattered read from the disk into a single large read of contiguous sectors and suppresses the unwanted data by inserting "no-operation" commands in place of the read commands during the transfer to the host.