Abstract: An ECL to TTL translator converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic translations. The ECL input signal is transformed into first and second differentially related currents which develop first and second voltages for biasing first and second switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage includes an upper and lower transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.

Abstract: A circuit for use in conjunction with an enable/disable gate of a three state logic circuit for disabling the outputs of the logic circuit during power up of the voltage supply to maintain a high impedance output state at the outputs of the logic circuits. The circuit includes a voltage level detector stage comprising a switching transistor that is held in a non-conducting state until the voltage supply reaches a predetermined potential after which the transistor is turned on and a pair of transistors configured as a current mirror with their bases coupled to the output of the switching transistor. The pair of transistors are turned on until the switching transistor is turned on to provide sufficient base current drive to a disable transistor of the enable/disable gate such that the logic circuit is disabled accordingly. An aspect of the invention is that the power up circuit draws little additional power during normal operation of the logic circuit.

Abstract: An Emitter-Coupled-Logic (ECL) bus driver circuit provides differential ECL output signals designed for bus driving applications in response to receiving differential logic input signals and when disabled by a disabling signal places the differential outputs in a low state wherein a high impedance is presented thereat. The circuit includes a single logic gate and enable/disable gate that places the logic circuit in the ECL tri-level state using incremental current in conjuction with the current drain of the logic gate to reduce current drain otherwise required. In addition, time delay through the bus driver circuit is maintained at a minimum since only one gate is required to provide the differential function.

Abstract: A method for trimming a diffused or implanted resistor located within an integrated circuit is disclosed. This technique for trimming a resistor requires the use of high current pulses and geometric shaped metal contacts. The current pulses react with the electropositive metal atoms in the thin film conductor and cause the metal atoms to migrate to another location, thus altering the value of the resistor by progressively decreasing the conductivity of the resistor.

Abstract: A complementary voltage comparator is described wherein a CMOS operational amplifier having an input stage comprising N-channel field effect transistors is coupled with a CMOS operational amplifier having an input stage comprising P-channel field effect transistors. The outputs of the operational amplifiers are converted to currents and combined to indicate the relative magnitudes of the voltages being compared. This configuration allows the range of input voltages to vary over the full range of supply voltages and negates the need for offset correction.

Abstract: A current mode logic gate for logically combining input logic signals is comprised of a first pair of transistors each having a base, collector and at least one emitter with the emitters being coupled together to a current source while the bases are respectively coupled to first and second inputs of the gate. At least one other pair of transistors are provided the bases of which are coupled to third and fourth inputs of the gate while the collectors are respectively coupled to first and second outputs of the gate. Each of the transistors of the other pair have first and second emitters with the first emitters being coupled to the collector of one of the transistors of the first pair of transistors while the second emitter of one of the transistors of the other pair is coupled to the collector of the other one of the first pair of transistors. The second emitter of the other one of the other pair of transistors is either left open-circuited or is shorted to its base.

Abstract: A voltage level conversion circuit manufacturable in a standard semiconductor process is provided wherein an output voltage having a magnitude greater than the supply voltage and greater than the gate oxide breakdown voltage of the MOS devices is produced. A voltage level shifter circuit alternately charges a pair of capacitors which in turn alternately charges a second pair of capacitors. The second pair of capacitors is coupled to the output to produce the shifted output voltage having a frequency that is double the frequency of the input to the voltage level shifter circuit.

Abstract: A circuit for providing multiple currents the ratios of which are constant and temperature independent. The circuit includes at least first and second transistors the bases of which are shorted together and whose emitters are interconnected via respective trimmable resistors to a thermal current supply. By driving the transistors with a thermal current and trimming one or the other or both resistors the current ratios can be adjusted and will remain constant as temperature is varied.