Abstract: A memory-efficient trellis coded quantizer divides consecutive trellis columns into groups or windows each containing the maximum number of columns for which each pair of columns in a window still retains statistical dependence with respect to the states of the column and in relation to any trellis path connecting the two columns. Back searching for code words operates on each individual window, rather than on the overall trellis. Windows are sequentially processed in pairs to derive the code words for the input that has been trellis coded. Required storage is reduced, since trellis and code word storage is required only for the windows currently being processed.

Abstract: A P-stage shift register or counter is added to the charge pump and/or to the phase frequency detector of a phase locked loop circuit to keep the output clock stable enough from the locked frequency value and available for long enough after the input reference clock has been removed. This mode is called the phase locked loop (PLL) free running mode (FRM) and is activated as soon as the device has detected the loss of the input reference clock of the phase locked loop. Once the free running mode is activated the charge pump automatically enters its high impedance state resulting in a slower frequency shift process at the PLL output in comparison to a conventional PLL. This main advantage of this PLL circuit is that the system clock is kept running for long enough so that the system can issue a fault report through another logic and memory device when the reference clock is suddenly removed either accidentally or not.