Abstract: A method of manufacturing a pre-molded leadframe for use in a semiconductor package includes providing a leadframe having a die pad and a plurality of leads. A first molding material is formed in the leadframe to expose the upper surface of the die pad and the upper surfaces of the plurality of leads.
Type:
Grant
Filed:
July 21, 2006
Date of Patent:
July 15, 2008
Assignee:
STATS ChipPAC Ltd.
Inventors:
Il Kwon Shim, Diane Sahakian, Kambhampati Ramakrishna, Seng Guan Chow
Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections.
Type:
Grant
Filed:
October 8, 1998
Date of Patent:
February 20, 2001
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Allen S. Yu, Patrick K. Cheung, Paul J. Steffan