Abstract: In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes a semiconductor substrate having buried contact landing pads and direct contact landing pads. A lower interlayer insulating layer is disposed on the semiconductor substrate. A plurality of parallel bit line patterns are disposed on the lower interlayer insulating layer to fill the direct contact holes. A passivation layer that conformally covers the lower interlayer insulating layer and the bit line patterns is formed. An upper interlayer insulating layer for covering the semiconductor substrate having the passivation layer is formed. Buried contact plugs are disposed in the upper interlayer insulating layer between the bit line patterns and extended to contact the respective buried contact landing pads through the passivation layer and the lower interlayer insulating layer.

Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.

Abstract: A synchronous semiconductor device and a method for preventing coupling between data buses. The synchronous semiconductor device supports at least two kinds of bit configuration modes and includes a first data bus and a second data bus. The first data bus is used to transmit data in a first bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode. The second data bus is used to transmit data in the first bit configuration mode and a second bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode and the second bit configuration mode. The first data bus and the second data bus are arranged alternately. In using the device and method, it is possible to prevent coupling between the data buses without additional shielding lines by using the same kind of data bus, which is not used to transmit data, as the shielding line.

Abstract: A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

Abstract: Provided are a semiconductor device having a sense amplifier driver and a method of generating a sense amplifier enable signal for enabling a sense amplifier. The semiconductor device includes a sense amplifier, which is comprised of a plurality of inverters which are connected in series, a power supply circuit, and a discharge circuit. In this semiconductor device, an enabling timing of the sense amplifier enable signal is controlled by delaying a time taken to evaluate a first dummy bit line from a power supply voltage to a ground voltage using parasitic capacitance between the first dummy bit line and a first complementary dummy bit line. The method of generating the sense amplifier enable signal is performed using the above-described sense amplifier.

Abstract: There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal.

Abstract: Provided is a method of forming a fine pattern, in which a silicon oxide layer is formed on a photoresist pattern and dry etching is performed on the resultant structure. According to the method, a photoresist pattern is formed on a material layer on which a fine pattern is to be formed, a silicon oxide layer is conformally deposited on the photoresist pattern without damaging the photoresist pattern, and dry etching is performed on a lower layer. During the dry etching, spacers are formed along the sidewalls of the photoresist pattern, and then, a polymer layer is formed on the photoresist pattern. Accordingly, it is possible to prevent the thinning of the photoresist pattern so that a desired pattern can be obtained, and further, to prevent striation or wiggling from occurring on the patterned material layer.

Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

Abstract: A branch prediction method using an address trace is described. An address trace corresponding to an executed instruction is stored itself with a decoded form. After appointing a start address and an end address of a repeated routine, current routine iteration count and total number of iterations are compared with each other, confirming the end of the routine and storing address information of the next routine. Therefore, access information of the repeated routine can be stored using a small amount of trace cache.

Abstract: In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.

Abstract: An embedded controller includes a central processing unit, a memory interface for interface with an external memory, and a function block or peripheral device with a register for storing operation state information. The peripheral device includes a detection circuit, a storage unit, for example in the form of a FIFO, a multiplexer, and a direct memory access (DMA) controller. The state detection circuit activates a flag signal whenever the operation state information of the register is varied, and the FIFO stores the operation state information from the register in response to the flag signal. The multiplexer is controlled by the DMA controller and transmits the operation state information of the FIFO to an internal bus. As a result, the operation state information of the FIFO is stored in the external memory through the memory interface.

Abstract: A source driver circuit and method for use in a thin film transistor liquid crystal display that can reduce the slew rate of color data includes a data latching unit for receiving and storing color data in response to a main clock signal, and outputting the stored color data in response to a predetermined first control signal; a switching buffering unit for receiving the color data output from the data latching unit, and applying the color data to a panel in response to a predetermined second control signal; and an output controller for generating the first and second control signals in response to the main clock signal, a polarity inversion signal that controls the polarity of voltage of the color data output to the panel, and the first clock signal. According to the source driver circuit and method, the slew rate of the color data, which is to be applied to a panel, can be reduced using the existing signals, without additionally making signals at the outside of a semiconductor chip.