Abstract: A fine-pitch hermetic device (10) can be manufactured wherein two sets of wire bonds (18 & 20) are used to electrically connect a semiconductor die (12) to a leadframe (16). Jumper leads or conductive pads (28) are placed on an inner surface of a ceramic base (14) to electrically interconnect the two sets of wire bonds. The jumper leads enables shorter wire lengths to be used. The leadframe is attached to the ceramic base with glass embed technology. A cap (22) is affixed to the base with a hermetic seal (24). The invention is also compatible with flip-chip dice and multichip modules.

Abstract: A low cost method is used to standardize testing of bare semiconductor devices. In one embodiment, a universal test circuit substrate (10) having an interleaving fan-out pattern of conductive traces (14) is provided. The radial array of conductive traces terminates in a plurality of test pads (16) placed in a standard pattern around a periphery of a central die accommodating region. A die cavity (36), slightly larger than the size of a semiconductor die (32) to be tested, is formed in the central die accommodating region. The semiconductor die is placed approximately centered in the die cavity and is wire bonded (40) to individual traces of the pattern of conductive traces. The die can be tested and burned-in on the universal test circuit substrate with a test probe making contact with the test pads. The universal test circuit substrate can accommodate a multiplicity of die sizes and pin-out requirements of semiconductor devices.

Abstract: A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.

Abstract: Dual field oxide isolation (34 & 42) is formed by oxidizing through a portion (44) of a silicon nitride layer (30), through an exposed portion (43) of a remaining portion (18) of a masking layer (16), and through an exposed portion (42) of a buffer layer (28), all of which overlie isolation regions (22) of the silicon substrate (12). The different portions vary the diffusion rate of oxygen so that different field oxide thicknesses are created in a single field oxidation cycle. Therefore, integrated circuits having both low voltage densely packed devices and high voltage devices can be fabricated on the same circuit.

Abstract: A quad leadframe (30) for a semiconductor device is made from multiple dual-in-line leadframes (10). Two dual-in-line leadframes (10) are provided, wherein each leadframe has two opposing siderails (12) with a plurality of leads (14) connected to those siderails. The leads have a metal clad layer (16) on lead tips which are distal to the two siderails. Each leadframe also has another two opposing siderails (18) which are not connected to any leads. The two leadframes are stacked on top of one another, wherein one leadframe is rotated by substantially 90.degree. with respect to the other leadframe such that the leads of one leadframe are perpendicular to the leads of the second leadframe to form a quad configuration. The siderails enable alignment of the leadframes to each other. The two leadframes can then be optionally tack welded together at any location along the siderails.

Abstract: A wire bonded semiconductor die in a plastic package having minimal or no wire sweep is provided in which the semiconductor device comprises two different encapsulants. The semiconductor die and the wires including the bonds are completely enveloped by a first encapsulating compound, such as an epoxy resin molding compound like Nitto Denko EP-6045. This first encapsulant serves to protect and lock the wires in an upright position so that no wire sweep occurs during the second encapsulation in which the package body is molded. A second encapsulating molding compound forms the package body through standard transfer molding technique with no modification to existing equipment.

Abstract: A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.

Abstract: Plastic encapsulated ICs (28) are susceptible to moisture due to the permeability of molding compounds. ICs (28) may be baked until dry before being shipped to the customer to reduce the risk of cracking. To retain this dry condition, ICs (28) are packaged and shipped in dry-packs. Compartmentalized humidity sensing indicators (14, 16 and 18) are provided for tape and reel IC shipping medium (20) to monitor moisture levels. The indicators (14, 16 and 18) are provided at multiple locations along the carrier tape (22) as a continuous strip with repeating series of humidity indicators. Distinction can be made between the humidity conditions along the length of the carrier tape, which allows identification of problem areas and affected devices. Thus, only portions of devices shipped in tape and reel need rebaking, which offers cycle time and cost advantages over rebaking the entire contents of the carrier tape.

Abstract: Electrical parasitic parameters can lead to reflections and switching noise in a circuit causing signal distortions. A stripline configuration semiconductor device (10) can be manufactured to reduce the overall parasitic parameters, especially inductance, of a device. In one embodiment, a semiconductor die (12) having a grounded backside (20) is directly bonded with an electrically conductive adhesive (22) to a metal base (16), thus grounding the metal base. The die is also electrically connected to a leadframe (14) by wire bonds (24). An electrically insulating adhesive (28) is used to seal a metal lid (18) to the metal base with the die and leadframe disposed between the lid and base, thus forming a protective package body. The lid is grounded to a ground lead (26) of the leadframe with a solder bridge (30). An additional advantage to having a metal package body is that it provides shielding for the device.

Abstract: A plastic land grid array semiconductor device (30) can be manufactured using conventional techniques. In one embodiment, a semiconductor die (12) having an active surface is provided. An LOC leadframe (14) is provided, wherein leads (16) have a horizontal portion (18) and a vertical portion (20). The active surface of the die is attached to the leads with an LOC tape (17) and is electrically connected to the horizontal portion by wire bonds (24). A plastic package body (32) is molded around the die, the wire bonds, and a portion of the leadframe. The vertical portion of the leads terminates and its thickness is exposed at a surface of the package body, thus forming a grid array of external electrical contacts. An insulative material (34) is coated on the sides of the package body to cover any exposed thickness of the horizontal portion of the leads.

Abstract: A thin semiconductor device (50) can be cost effectively manufactured using conventional wire bonding technology and stamped leadframes. A flagless leadframe (12) is utilized in one embodiment. A support tape (14) having a die support surface (20) is attached transversely to a plurality of leads (18) of the leadframe. A semiconductor die (16) is attached on its active surface to the die support surface such that the active surface is coplanar with the leadframe. Low loop wire bonds (24) electrically connect the die to the leadframe. A resin encapsulant package body (52) is molded around the active surface of the die, the wire bonds, and a portion of the leads. An inactive surface of the die is exposed for enhanced thermal dissipation in addition to enabling a thin package body. External lead configuration of the semiconductor device is not limited.

Abstract: An area array semiconductor device (10) having a lid with functional I/O contacts can be manufactured. In one embodiment, a semiconductor die (12) is mounted in a die cavity (16) of a substrate (14). A plurality of wire bonds (20) connect the die to conductive traces (18) on a surface of the substrate. A lid (22) having conductive traces (26) on an inner surface, which are electrically interconnected to an area array of contact pads (28) on an outer surface by a plurality of plated through-holes (30), is attached to the substrate with an anisotropic conductive adhesive (32). The adhesive electrically connects the conductive traces on the substrate to the conductive traces on the lid. A plurality of conductive pins (34) are attached to the area array of contact pads to provide one method of mounting the device to a board.

Abstract: Plastic encapsulated semiconductor devices are susceptible to moisture due to the permeability of molding compounds. Devices may be baked until dry before being shipped to the customer to reduce the risk of cracking. To retain this dry condition, devices are packaged and shipped in dry-packs. A vacuum seal indicator (18) for flexible material enables a user to determine the integrity of a vacuum seal. The seal indicator has a quick recognition pattern composed of either negative (22) or positive (24) features or a combination thereof, and is placed inside a dry-pack bag (30) which is vacuum sealed prior to shipping. The integrity of the vacuum seal can be determined by looking at the dry-pack bag to see whether the recognition pattern is sharply defined against the bag or not. The vacuum seal indicator can be used in conjunction with any shipping media (28) as long as the outer bag is flexible.

Abstract: A semiconductor multiple package module (10) on a PCB material substrate (18) is provided, wherein semiconductor dice are directly mounted onto the PCB material substrate (18) thereby eliminating a subsequent board mounting at the customer level. A plurality of semiconductor dice are mounted and electrically connected to a plurality of circuit traces (22) on the PCB material substrate (18) having a plurality of edge connectors (20). The plurality of circuit traces (22) has conductive paths to electrically interconnect the semiconductor dice to the edge connectors (20) and to each other. The semiconductor dice are directly overmolded on the PCB material substrate (18) with a molding compound to form individual semiconductor devices (12, 14, and 16) having separate package bodies. The individualized package bodies enable repair to the module by making removal of only nonfunctional semiconductor devices from the PCB material substrate (18) possible.