Patents Represented by Attorney Mnemoglyphics, LLC
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Patent number: 8312198Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).Type: GrantFiled: January 24, 2012Date of Patent: November 13, 2012Assignee: Intel CorporationInventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnandan Kaushik, Luke Hood
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Patent number: 8296546Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.Type: GrantFiled: January 11, 2012Date of Patent: October 23, 2012Assignee: Intel CorporationInventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg
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Patent number: 8291168Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: December 31, 2011Date of Patent: October 16, 2012Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Patent number: 8281109Abstract: A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.Type: GrantFiled: December 27, 2007Date of Patent: October 2, 2012Assignee: Intel CorporationInventors: Robert Valentine, Doron Orenstein, Bret Toll
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Patent number: 8276149Abstract: Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.Type: GrantFiled: May 19, 2010Date of Patent: September 25, 2012Assignee: Intel CorporationInventors: David W. Burns, K. S. Venkatraman
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Patent number: 8244980Abstract: A method and apparatus for improving shared cache performance. In one embodiment, the present invention includes a cache having multiple ways. A locality tester measures a first locality of a first process and second locality of a second process. A first set of multiple ways stores the data used by the first process and a second set of multiple ways stores the data used by the second process, where the second set is a superset of the first set.Type: GrantFiled: June 21, 2006Date of Patent: August 14, 2012Assignee: Intel CorporationInventor: Tryggve Fossum
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Patent number: 8230172Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: GrantFiled: December 3, 2009Date of Patent: July 24, 2012Assignee: Intel CorporationInventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Patent number: 8225046Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to track consecutive misses to ways of a cache, i.e. hits/reads to other ways of cache. Based on the usage of ways and the non-usage of other ways, the way predicting logic determines if a way is to be powered down. In response to determining a way is to be powered down, the way predicting logic generates a power signal to power down an associated. Furthermore, upon a subsequent hit to a powered down way, the way predicting logic toggles the power signal to power up the associated way to ensure performance.Type: GrantFiled: September 29, 2006Date of Patent: July 17, 2012Assignee: Intel CorporationInventors: Martin Licht, Jonathan Combs, Andrew Huang
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Patent number: 8209490Abstract: The present application is a protocol for maintaining cache coherency in a CMP. The CMP design contains multiple processor cores with each core having it own private cache. In addition, the CMP has a single on-ship shared cache. The processor cores and the shared cache may be connected together with a synchronous, unbuffered bidirectional ring interconnect. In the present protocol, a single INVALIDATEANDACKNOWLEDGE message is sent on the ring to invalidate a particular core and acknowledge a particular core.Type: GrantFiled: December 30, 2003Date of Patent: June 26, 2012Assignee: Intel CorporationInventors: Matthew Mattina, George Z. Chrysos
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Patent number: 8185571Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: March 23, 2009Date of Patent: May 22, 2012Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 8171321Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.Type: GrantFiled: December 26, 2007Date of Patent: May 1, 2012Assignee: Intel CorporationInventors: Arvind Kumar, Per Hammarlund, Glenn Hinton, Johan G. Van De Groenendaal
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Patent number: 8161269Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.Type: GrantFiled: March 24, 2011Date of Patent: April 17, 2012Assignee: Intel CorporationInventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
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Patent number: 8103830Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: September 30, 2008Date of Patent: January 24, 2012Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Patent number: 8103816Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).Type: GrantFiled: October 28, 2008Date of Patent: January 24, 2012Assignee: Intel CorporationInventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnanda Kaushik, Luke Hood
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Patent number: 8099581Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.Type: GrantFiled: June 30, 2009Date of Patent: January 17, 2012Assignee: Intel CorporationInventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh Madukkaraumukumana, Camron Rust, Sebastian Schoenberg
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Patent number: 8060974Abstract: Embodiments of foot-worn scrubbing apparatus are disclosed. One embodiment of the apparatus includes a sole made of a suitable sponge material and having a top surface and a bottom surface. A scrubbing surface of another suitable scrubbing material is adhered to the bottom surface of the sole. The sole is also attached to a thong in order to secure the sole and the scrubbing surface to a bare foot or to a socked foot of a user.Type: GrantFiled: December 6, 2010Date of Patent: November 22, 2011Inventor: Lisa K. McLogan
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Patent number: 7845043Abstract: Embodiments of foot-worm scrubbing apparatus are disclosed. One embodiment of the apparatus includes a sole made of a suitable material and having a top surface and a bottom surface. A scrubbing surface of another suitable material is adhered to the bottom surface of the sole. The sole is also attached to a thong in order to secure the sole and the scrubbing surface to a bare foot or to a socked foot of a user.Type: GrantFiled: March 10, 2007Date of Patent: December 7, 2010Inventor: Lisa K. McLogan