Abstract: In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.

Abstract: A magnetic random access memory (MRAM) device is provided which includes a field-inducing line with a first layer having a plurality of dielectrically spaced conductive segments and a second layer having a conductive portion in contact with at least two of the dielectrically spaced conductive segments. A method for fabricating such a field-inducing layer may include patterning a conductive layer to form the first layer and depositing another conductive layer above at least a portion of the first layer to form the second layer. In some cases, a surface of a first lateral portion of the field-inducing line substantially aligned with a magnetic junction of the device may include a cladding layer, while a surface of a second portion of the field-inducing line substantially aligned with a spacing arranged adjacent to the magnetic junction may be substantially absent of a cladding layer.

Abstract: A system and method is described for event-driven data transformation. Generally, the system and method is directed to a transformation engine that iterates through one or more data sources, transforms data received from the data sources, and stores the output to one or more data targets. More specifically, the transformation engine is driven by executing specified event actions upon occurrence of specified triggering events. Thus, flexible, adaptable, highly tailored transformations can be implemented without incurring the often substantial expense of developing customized point-to-point solutions from scratch. The present invention supports one-to-one mappings, many-to-one mappings, one-to-many mappings, and many-to-many mappings. In addition, the present invention supports both hierarchical and flat data sources and targets.

Abstract: A method is provided which includes creating a plasma from a gas mixture including diatomic nitrogen gas and a gas comprising silicon. In addition, the method includes exposing a microelectronic topography to the plasma to form a silicon nitride layer thereon. In some cases, the method may include forming the silicon nitride layer at a temperature less than approximately 300° C. Furthermore, the method may include subsequently processing the microelectronic topography at a temperature greater than or equal to approximately 250° C. such that a stress change of less than approximately 1.0×1010 dynes/cm2 occurs within the silicon nitride layer. In addition, a microelectronic topography is provided which has a silicon nitride layer with a concentration of diatomic hydrogen that is at least one order of magnitude lower than a concentration of diatomic hydrogen within a silicon nitride layer formed from a plasma generated from ammonia.

Abstract: A method for fabricating a bipolar transistor is provided. In some cases, the method may include patterning an epitaxial layer to expose one or more regions of a semiconductor topography. The method may further include depositing an intermediate layer above the exposed regions and remaining portions of the epitaxial layer. A conductive emitter structure may then be formed above and within the intermediate layer. In another embodiment, the method may include etching a first dielectric layer in alignment with a patterned base of a bipolar transistor while simultaneously etching a second dielectric layer in alignment with a patterned emitter structure of the bipolar transistor. In yet other embodiments, the method may include depositing an intermediate layer which is substantially etch resistant to a resist stripping process. In addition or alternatively, the intermediate layer may include etch characteristics that are substantially similar to a conductive layer formed above the intermediate layer.

Abstract: A magnetic memory cell and method for improving the write selectivity of memory cells in an MRAM array is provided herein. In particular, the magnetic memory cell may have a magnetic layer with a shape that is substantially asymmetrical about at least one axis of the magnetic layer. Such asymmetry may advantageously reduce and/or eliminate the effects of variations in the fabrication process. In addition, an asymmetrical memory shape may induce a relatively consistent equilibrium vector state, allowing a single switching mechanism to set the magnetic direction of the cell. Furthermore, a method is provided for programming a memory cell, in which the amount of current needed during a writing procedure is advantageously reduced relative to the amount of current needed in conventional writing procedures. In this manner, the asymmetrical memory cell and method produces a storage medium having overall power requirements less than those associated with symmetrical memory cells.

Abstract: A system and method is described for event-driven data transformation. Generally, the system and method is directed to a transformation engine that iterates through one or more data sources, transforms data received from the data sources, and stores the output to one or more data targets. More specifically, the transformation engine is driven by executing specified event actions upon occurrence of specified triggering events. Thus, flexible, adaptable, highly tailored transformations can be implemented without incurring the often substantial expense of developing customized point-to-point solutions from scratch. The present invention supports one-to-one, mappings, many-to-one mappings, one-to-many mappings, and many-to-many mappings. In addition, the present invention supports both hierarchical and flat data sources and targets.

Abstract: A CMP system, a wafer carrier, and components of a wafer carrier are provided for processing a semiconductor topography. In particular, a CMP system, a wafer carrier, and components of a wafer carrier are provided in which a greater pressure may be applied in a first portion of a semiconductor topography than in a second portion of the topography. The first portion may, for example, be adjacent to an outer edge of the topography, while the second portion may include the center of the topography. Alternatively, the first portion and second portion of the semiconductor topography may include any region of the topography. The wafer carrier components may include a carrier plate and/or a carrier backing film adapted to apply a greater pressure in a first portion of the semiconductor topography than in a second portion of the semiconductor topography.

Abstract: A microelectromechanical device is provided which includes a contact structure interposed between a pair of electrodes arranged beneath a beam. In some embodiments, the device may include additional contact structures interposed between the pair of electrodes. For example, the device may include at least three contact structures between the pair of electrodes. In some embodiments, the beam may be suspended above the pair of electrodes by a support structure affixed to a first end of the beam. Such a device may further include an additional support structure affixed to a second end of the beam. In some cases, the device may be adapted to pass a signal from the first end to the second end of the beam. In addition or alternatively, the device may be adapted to pass the signal between one or both ends of the beam and one or more of the contact structures.

Abstract: An improved furnace system and method is provided to substantially minimize, if not eliminate, ambient air from entering a heated chamber of the furnace system during a critical processing step. The furnace system can be used in, for example, an oxidation step where ambient air containing oxygen is prevented from entering an atmospheric pressure tube by essentially purging potential leak areas with an inert gas, such as nitrogen, at the critical moment during temperature ramp up and ramp down, and prior to temperature stabilization and the introduction of an oxidizing gas. If oxygen is not present within the tube, then a tungsten sidewall surface of a gate conductor, for example, will not inadvertently oxidize at the critical pre- and post-oxidation moments. However, if steam is present where hydrogen is available with oxygen, the underlying polysilicon sidewall surface will selectively oxidize instead of the overlying tungsten.