Abstract: A computer graphics system is provided that includes a memory to store image data, a bin pointer list to store information regarding a plurality of image subscenes, and a pointer cache system to maintain data regarding the plurality of image subscenes. The pointer cache system may include a tag array section, a data array section and a decoupling section.

Abstract: Provided are a method, system, and program for processing packets of data. An available packet buffer in memory is allocated to a received packet, wherein the received packet is stored in the allocated packet buffer. A determination is made as to whether a number of available packet buffers is less than a first threshold. A further determination is made as to whether the number of available packet buffers is less than a second threshold if the number of available packet buffers is not less than the first threshold. An operation is initiated to copy the received packet from the allocated packet buffer to a copy buffer if the number of available packet buffers is less than the second threshold.

Abstract: Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus environment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.

Abstract: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus.

Abstract: A digital broadcast signal is received to a digital television receiver in a computer. The digital broadcast signal is processed to extract enhanced content data. The enhanced content data is stored in a web browser cache. The web browser cache is interrogated with an application programming interface. Responsive to the application programming interface interrogating the web browser cache, the enhanced content data is provided to a personal web server. The enhanced content data in the personal web server is stored and providing to at least one client device.

Abstract: In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

Abstract: For a client seeking network resources from a network site, such as a web page, audio, visual, or other data, where the network site's desired network resources are also provided by mirroring network hosts, measurements are made to determine a communication efficiency between the client and the network site and mirroring network hosts. The client is then directed to communicate with the network site or a mirroring network host according to which had the highest measured communication efficiency with the client. In such fashion, real time adjustments can be made so as to more optimally distribute client network resource requests across all available sources of the desired network resources, and provide for real time load balancing and fail over of disabled hosts.

Abstract: A system which allows modular expansion to provide additional services to high speed data. A high speed data line such as DSL or cable is input to a broadband expandable modem device. The modem device produces an output indicative of the data within the data stream. An expansion output is indicative of voice within the data stream which is separated from the data. The expansion output is coupled to one of a plurality of voice adapters. Each of the voice adapters is expandable so daisy chain communication is possible to add additional layers of voice by simply acquiring additional voice adapters. The system preferably uses USB for the expansion capability.

Abstract: An apparatus in accordance with the invention includes a switch-box, where the switch-box includes a memory buffer to which information is copied from a computing system selected via the switch-box from two or more computing systems coupled with the switch-box as a result of a first substantially predetermined event.

Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.

Abstract: Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus enviroment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.

Abstract: In an encoding or decoding process for compressible data, non-raster ordered bitstreams of transform data are rearranged in memory so later data access is contiguous, efficiently allowing processing in a single cache line. In an encoder, rearrangement can utilize a buffer copy that enables address calculation to performed only once per block.

Abstract: A method of and an apparatus for designing a test environment and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated. An adjustment might be made to the virtual calibration of the virtual test environment and/or to the virtual device, or both, and the design of the actual device might be improved. The invention can be implemented on a properly programmed general purpose processing system or on a special purpose system.

Abstract: Embodiments of a method and apparatus for improving bus utilization, such as for transferring data to a modem, for example, are described.

Abstract: A method of abstracting information through object interfaces is described. The object interfaces are used to present platform device information in a pre-boot service environment. Firmware tables such as Advanced Configuration and Power Interface and System Management Basic Input/Output System may be used to auto-configure diagnostic test suites through an abstracted software interface.