Patents Represented by Attorney Morrsion & Foerster LLP
  • Patent number: 7943166
    Abstract: Compositions are provided that contain a TRPV1 agonist, such as capsaicin, and a solvent system. Topical application of the composition results in rapid delivery of agonist to the dermis and epidermis. Method of using the compositions for reducing nociceptive nerve fiber function in subjects, and for treatment of capsaicin-responsive conditions are also provided.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: May 17, 2011
    Assignee: Neurogesx, Inc.
    Inventors: Naweed Muhammad, Gene C. Jamieson, Keith R. Bley, Sanjay Chanda
  • Patent number: 7249847
    Abstract: An eyeglass lens and manufacturing method using epoxy aberrator includes two lenses with a variable index material, such as epoxy, sandwiched in between. The epoxy is then cured to different indexes of refraction that provide precise corrections for the patient's wavefront aberrations. The present invention further provides a method to produce an eyeglass that corrects higher order aberrations, such as those that occur when retinal tissue is damaged due to glaucoma or macular degeneration. The manufacturing method allows for many different applications including, but not limited to, supervision and transition lenses.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: July 31, 2007
    Assignee: Ophthonix, Inc.
    Inventor: Andreas W. Dreher
  • Patent number: 7006371
    Abstract: A semiconductor memory device comprises a memory array in which memory cells having variable resistive elements (R11 to Rij) whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released and selection transistors (T11 to Tij) comprising N type MOSFETs are arranged with a matrix; programming means for applying the electrical stress to the variable resistive elements (R11 to Rij) to program data into the memory cell; programming state detection means for detecting the variation in the electrical resistance at the time of the programming operation; and programming control means for stopping the application of the electrical stress when the electrical resistance is varied to a predetermined reference value. With this structure, it is possible to constitute the semiconductor memory device in which the time required for programming data is shortened and the programming precision is high.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: February 28, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuaki Matsuoka