Abstract: Methods of forming bipolar junction transistors include the step of forming insulated gate electrode means adjacent the base region of the transistor so that the majority carrier conductivity of the base region and the gain (.beta.) of the transistor can be modulated in response to a gate bias. The methods can include the steps of forming an insulated gate electrode containing a conductive gate on a face of a substrate and then forming a base region in the substrate. These steps can then be followed by the steps of patterning the insulated gate electrode to define an opening which exposes a first portion of the base region at the face and then forming an emitter electrode in the opening. The emitter electrode and conductive gate are preferably formed to be in electrical contact so that during operation, the potential of the emitter electrode and conductive gate are maintained at the same level.

Abstract: A solid state imaging device includes a light receiving portion having a first photodiode and a second photodiode whose potential well is deeper and whose photosensitivity is lower than that of the first photodiode, and a transmitting portion having a first transmitting gate for transmitting charges accumulated in the first photodiode to a transmission device and a second transmitting gate for transmitting charges accumulated in the second photodiode to the transmission device. Thus, the dynamic range of the solid state imaging device becomes wider.

Abstract: The invention is directed to a method and apparatus for covering open-top truck trailers used to haul wood chips and the like. A flexible cover is pulled over the open top of a trailer via a shaft rotatable between a first and second position; a projection extending from the shaft and configured to engage the flexible cover when the shaft is in a first position and to disengage the flexible cover when the shaft is in a second position; and a counterweight extending from said shaft and configured to rotate the shaft from a second position to a first position.

Abstract: An integrated circuit memory device includes a plurality of memory units arranged in an array of columns and banks. Each of the memory units includes a memory cell, and a bit line coupled to the memory cell wherein the bit line receives a bit of information from the memory cell. Each of a plurality of global column selection lines extends along a respective column of the memory units through each of the banks. A column decoder generates global column selection signals on the plurality of global column selection lines. Each of a plurality of input/output lines extends along a respective bank of the memory units. In addition, each of a plurality of memory unit selection circuits connects a respective bit line of a respective memory unit to a respective input/output line in response to a global column selection signal on the respective global column selection line and a bank selection column address signal.

Abstract: An input logic signal buffer circuit includes a differential amplifier which is responsive to an input logic signal and to a reference signal, to produce an output logic signal at an output node thereof. The input logic signal buffer circuit also includes a bypass amplifier which is electrically connected between the output logic signal and the output node. The bypass amplifier supplies additional current to the output node in response to logic level transitions of the input logic signal. The bypass amplifier preferably is a field effect transistor, the gate of which is electrically connected to the input logic signal and the source and drain of which are serially connected between the output node and a current limiting resistor. Logic level transitions with reduced delays, particularly at low power supply voltages, are thereby provided.

Abstract: An integrated circuit memory device includes a pair of bit lines, a memory cell connected to one of the bit lines, a sense amplifier connected between the bit lines, and a sense amplifier control circuit. The sense amplifier control circuit generates a sense amplifier drive signal on a sense amplifier drive node responsive to an enable signal. The sense amplifier control circuit includes a comparison circuit, a drive circuit, and a driver. The comparison circuit generates a comparison signal in response to a comparison of the sense amplifier drive signal and a predetermined reference signal, and in response to the enable signal. The drive circuit generates a gating signal in response to the comparison signal and in response to a magnitude of the sense amplifier drive signal so that the gating signal has a first magnitude when the sense amplifier drive signal is below a predetermined threshold and a second magnitude when the sense amplifier drive signal is above the predetermined threshold.

Abstract: Methods of forming field effect transistors having oxidation-controlled gate lengths include the steps of forming an insulated gate electrode on a face of semiconductor substrate. The gate electrode has exposed ends thereof which define an initial gate length. Source and drain region dopants are then implanted into first portions of the face, using the insulated gate electrode as an implant mask. The implanted first portions of the face and the exposed ends of the insulated gate electrode are then thermally oxidized to form a relatively thick oxide layer. During this step, the implanted dopants are diffused and bird's beak oxide extensions are formed at the upper and bottom corners of the gate electrode. The bird's beak oxide extensions are preferably formed to increase the separation distance between the gate electrode and the source and drain regions and thereby reduce the gate-source/drain capacitance and inhibit parasitic hot electron injection from the drain region.

Abstract: A method of screening a cell for the onset of senescence or a senescent state therein comprises detecting a p21-E2F complex in the cell, an elevation in the complex as compared to a normal cell indicating the onset of senescence or a senescent state in the cell. Isolated complexes comprised of p21 and E2F are also disclosed. The complexes stably bind to DNA and are useful, among other things, for binding DNA.

Abstract: A integrated circuit field effect transistor is formed with device isolation regions disposed on opposite sides of the transistor, each of which include a shallow insulation-filled trench region which abuts an insulating region underlying an active region of the transistor. A pair of spaced apart insulation-filled trench regions are formed in a semiconductor substrate at a surface of the substrate. An insulated gate is formed on the substrate between and separated from the insulation-filled trench regions. Spaced apart source and drain insulating regions are formed in the substrate, a respective one of which is disposed between the insulated gate and a respective one of the insulation-filled trench regions. Corresponding spaced apart source and drain regions are then formed on the spaced apart source and drain insulating regions. The insulated gate is formed overlying a channel region disposed between lightly doped source and drain regions.

Abstract: Forming power semiconductor devices having insulated gate bipolar transistor cells and freewheeling diodes cells includes forming an array of emitter regions of second conductivity type (e.g., P-type) in a cathode layer of first conductivity type (e.g., N-type) and forming a base region of first conductivity type on the cathode layer. An insulated gate electrode(s) pattern is formed on a surface of the base region and used as an implant mask for forming interleaved arrays of collector and anode regions of second conductivity type in the base region. An array of source regions of first conductivity type is formed in the collector regions, but not the anode regions, by implanting/diffusing source region dopants into the collector regions. To achieve preferred device characteristics, the array of collector regions is formed to be diametrically opposite the array of emitter regions to define a plurality of vertical IGBT cells.

Abstract: A structural rebar of the present invention comprises: an inner core formed by pultruding reinforcing fibers of a first reinforcing material through a bath or injection system of a first resin material; and an outer cladding comprising an inner cladding layer and an outer cladding layer. The inner core contains at least about 40 percent by weight reinforcing fibers of the first reinforcing material. The inner cladding layer comprises a second resin material reinforced with reinforcing fibers of a second reinforcing material. The fibers of the second reinforcing material are preferably unidirectional and oriented substantially parallel to the fibers of the first reinforcing material. The outer cladding layer comprises a corrosion-resistant third resin material reinforced with a third reinforcing material. Rebar of this configuration can have sufficient strength, rigidity, and corrosion resistance to be suitable for use in cementitious structural members.

Abstract: A buried bit line DRAM cell includes an active region having a protruding tap, formed in a semiconductor substrate. A device isolation region is formed in the substrate, outside the active region. A bit line laterally contacts the tap and is buried in the device isolation region. Accordingly, photolithography steps for forming a device isolation film twice and for forming a bit line contact can be omitted, thereby obtaining process simplicity and wider process margins.

Abstract: A roll system for use particularly in a papermaking press nip for dewatering a fibrous web, comprising a roll disposed so as to rotatingly cooperate with another roll in a press nip, the roll having a helical sensor for sensing pressure exhibited on the roll, and transmitting pressure signals to a processor as the roll rotates. Trigger signals are generated at certain times as the roll rotates, the time of the occurrence of the trigger signal representing a specific location on the helical sensor. The pressure signals are coordinated with the trigger signals, such that the pressure corresponds to the angular position of the roll where it is sensed. The operator may thus be given a visual or audible indication of the existence of non-uniformities in pressure sensed at various locations along the roll, thereby enabling corrective action to be initiated if necessary.

Abstract: An integrated circuit memory device includes a plurality of memory banks. Each of the memory banks includes a first array of at least four memory blocks and a second array of at least four memory blocks wherein each of the memory blocks includes at least two bit lines. Each of the memory blocks from the second array is paired with a respective memory block from the first array and the memory blocks are activated as pairs with at least one pair being activated during a data access operation. Four data lines are provided adjacent the first and second arrays of memory blocks. A plurality of input/output lines directly connects two of the bit lines from each of the memory blocks with two of the input/output lines so that for any pair of the memory blocks, two bit lines from each memory block of the pair are connected to separate data lines.

Abstract: Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g.

Abstract: A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region.

Abstract: In a method of storing directory information in a cellular radiotelephone, the cellular radiotelephone system is provided with a network directory database including a plurality of telephone numbers. The user is prompted for the input of search criteria, and the input search criteria is accepted. A search request data signal is generated in response to the input search criteria, and this signal is sent to the cellular system. The network directory database is searched for a match with the search criteria, and one or more telephone numbers can be identified. These telephone numbers are returned to the radiotelephone and stored in a memory of the radiotelephone. This method eliminates the need to interact with a directory assistance operator and reduces the time of connection between the radiotelephone and the cellular system.

Abstract: A depleted base transistor with high forward voltage blocking capability includes cathode and anode regions on opposite faces of a semiconductor substrate, a base region therebetween, a rectifying junction for depleting a portion of the base region of majority free carriers and an insulated gate electrode in a trench for modulating the conductivity of the depleted portion of the base region. The regions are formed as a vertical stack of semiconductor layers with the anode region (e.g., P+) as the bottom layer, the buffer region (e.g., N+) on the anode region, the drift region/e.g., N-) on the buffer region, the blocking voltage enhancement region (e.g., N-) on the drift region and the cathode region (e.g., N+) as the top layer on the blocking voltage enhancement region.