Patents Represented by Attorney, Agent or Law Firm Myers Bigel Sibley & Sajvoec
  • Patent number: 7364955
    Abstract: Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Yu-Gyun Shin
  • Patent number: 6730986
    Abstract: Bipolar junction transistors utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. A bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type in a semiconductor substrate. A trench is also provided in the substrate. This trench extends adjacent the intrinsic collector region. A base electrode of second conductivity type is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: May 4, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-Wook Park
  • Patent number: 6518157
    Abstract: An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: February 11, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gee-won Nam, Gi-jong Park, Hong-kyu Hwang, Jun-shik Bae, Young-rae Park, Jung-yup Kim, Bo-un Yoon, Sang-rok Hah