Patents Represented by Attorney Naomi Obinata
  • Patent number: 6051344
    Abstract: A photolithography method for creating very small line dimensions includes making a mask by exposing a mask blank through a reticle in a reduction photolithography exposure tool, at a reduction of N. The fabricated mask is then placed in a second photolithography exposure tool at a second reduction M, to expose a wafer substrate at a reduction of M. The resulting patterned substrate will have a critical dimension equaling the critical dimension of the original reticle, divided by the factor N times M. In this manner, very small size patterns can be created even though a larger pattern starting reticle is used.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: April 18, 2000
    Assignee: Intel Corporation
    Inventors: Joseph C. Langston, Patrick M. Troccolo
  • Patent number: 6040628
    Abstract: A structure and method of fabrication of a semiconductor integrated circuit is described. A first patterned electrically conductive layer contains a low dielectric constant first insulating material such as organic polymer within the trenches of the pattern. A second insulating material such as a silicon dioxide or other insulating material having a greater mechanical strength and thermal conductivity and a higher dielectric constant than the first insulating material is formed over the first patterned electrically conductive layer. Vias within the second insulating material filled with electrically conductive plugs and a second patterned electrically conductive layer may be formed on the second insulating material. The structure can be repeated as many times as needed to form a completed integrated circuit.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: March 21, 2000
    Assignee: Intel Corporation
    Inventors: Chien Chiang, David B. Fraser
  • Patent number: 5958629
    Abstract: A silicon-substrate based reflective photolithographic mask fabrication technique is described. The process begins with a multilayer, resonant reflecting substrate. A thin layer of silicon dioxide or other material capable of acting as an etch stop layer is deposited thereon. Then, a transmissive layer is deposited on the thin layer of etch stop layer. The transmissive layer is substantially transmissive to the wavelength of light used in the photolithography as well as capable of being selectively etched relative to the underlying etch stop layer. Then, the transmissive layer is etched to open preselected, absorptive areas. An absorptive layer is then deposited thereon. The absorptive layer is substantially absorptive to the wavelength of light used as well as capable of completely filling the opened areas of the transmissive layer. The absorptive layer is then planarized, and a thin protective cap is deposited thereon.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: September 28, 1999
    Assignee: Intel Corporation
    Inventors: Pei-Yang Yan, Guojing Zhang, Joseph Langston
  • Patent number: 5935733
    Abstract: A novel mask for photolithography in semiconductor processing and fabrication method is disclosed. The mask includes a layer of transmissive material transparent to the wavelength of light to be used deposited thereon. The transmissive material is plasma etched in accordance with a pattern in photoresist deposited thereon to create trench portions in the transmissive material. A layer of absorbing material absorptive to the wavelength of light to be used is deposited within the trench portions. The surface of the mask is then planarized to create a substantially smooth mask layer having trench portions in the transmissive material and absorbing layer portions within the trench portions. If desired, a second layer of transmissive material can be deposited over the smooth mask layer to provide a protective cap to create an overall smooth, flat completed mask surface. The mask is useful for transmissive photolithography applications as well as reflective photolithography applications.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: August 10, 1999
    Assignee: Intel Corporation
    Inventors: Charles R. Scott, Patrick M. Troccolo
  • Patent number: 5935737
    Abstract: During the fabrication of a photolithography mask, double defect-absorbing layers are incorporated to ensure the final mask structure is free of defects. The process begins with a resonant reflector substrate. First and second defect-absorbing layers cover the substrate. The first and second defect-absorbing layers are selected to be repairable if defects form, as well as can be etched selectively relative to each other as well as to the underlying substrate. The first defect-absorbing layer is coated with photoresist. The photoresist is patterned using photolithography. Next, the photoresist pattern is transferred to the first defect-absorbing layer through plasma etching. Any defects arising from the etching step are repaired. Next, the pattern formed in the first defect-absorbing layer is transferred to the second defect-absorbing layer, using the first defect-absorbing layer as a mask. Any defects arising from the etching step are repaired.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: August 10, 1999
    Assignee: Intel Corporation
    Inventor: Pei-Yang Yan
  • Patent number: 5928817
    Abstract: A novel mask for photolithography in semiconductor processing and the mask fabrication method is disclosed. The mask includes a substrate, a patterned buffer layer, a patterned absorber layer above the patterned buffer layer, and a protective cap. The substrate preferably contains a multilayer resonant reflective surface. The buffer layer and protective cap are transmissive to the wavelength of light used in the photolithography. The absorber layer is absorptive to the wavelength of light used in the photolithography. The mask is fabricated by first depositing the buffer layer. The absorber layer is formed on the buffer layer. Both absorber layer and buffer layer are etched to create a pattern. A protective cap layer is then deposited on the patterned absorber layer and buffer layer, and the protective cap is planarized as needed to create a substantially smooth mask surface.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: July 27, 1999
    Assignee: Intel Corporation
    Inventors: Pei-Yang Yan, Guojing Zhang
  • Patent number: 5858843
    Abstract: A method of forming a field effect transistor structure for making semiconductor integrated circuits is disclosed. The method utilizes a novel processing sequence where the high temperature processing steps are carried out prior to the formation of the gate dielectric and gate electrode. The process sequence proceeds as follows: A mask patterned in replication of a to-be-formed gate is deposited onto a substrate. Then, a high temperature step of forming doped regions is performed. Then, a high temperature step of forming a silicide is performed. Next, a planarization material is deposited over the mask and is planarized. The mask is removed selectively to the planarization material to form an opening within the planarization material. The gate dielectric and gate electrode are formed within the opening.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: January 12, 1999
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David B. Fraser
  • Patent number: 5795684
    Abstract: A novel mask for photolithography in semiconductor processing and fabrication method is disclosed. The mask includes a layer of transmissive material transparent to the wavelength of light to be used deposited thereon. The transmissive material is plasma etched in accordance with a pattern in photoresist deposited thereon to create trench portions in the transmissive material. A layer of absorbing material absorptive to the wavelength of light to be used is deposited within the trench portions. The surface of the mask is then planarized to create a substantially smooth mask layer having trench portions in the transmissive material and absorbing layer portions within the trench portions. If desired, a second layer of transmissive material can be deposited over the smooth mask layer to provide a protective cap to create an overall smooth, flat completed mask surface. The mask is useful for transmissive photolithography applications as well as reflective photolithography applications.
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: August 18, 1998
    Assignee: Intel Corporation
    Inventor: Patrick M. Troccolo
  • Patent number: 5514247
    Abstract: Disclosed is a process for plasma etching a mask patterned dielectric film to form vias on a semiconductor wafer, so that the resulting etched structure is devoid of residues on the walls of the structure. A via is an opening through a dielectric material through which a point of contact of underlying metal with a metal film deposited over the dielectric is made. The underlying metal, when exposed to plasma, has a tendency to sputter onto the vertical wall portions of the contact via structures. The metal-containing sputtered material forms a residue that essentially cannot be removed in the subsequent photoresist stripping process typically used in semiconductor manufacturing. The plasma etch process in accordance with the invention enables removal of the sputtered metal by utilizing with the basic dielectric etch gases a gas that reacts with the metal to form volatile compounds which are readily evacuable.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: May 7, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Hongching Shan, Robert Wu
  • Patent number: 5447409
    Abstract: A robot assembly, including a central hub, has two arms arranged for independent rotation about the hub. Two carriers, oriented 180.degree. apart from each other, are coupled to an end of each of the arms. A drive is provided for rotating the arms in opposite directions to extend one or the other of said carriers radially from said central hub, and for rotating the arms in the same direction to effect rotation of the carriers.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: September 5, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Howard Grunes, Avi Tepman, Robert Lowrance