Patents Represented by Attorney, Agent or Law Firm Nawrochi, Rooney & Siverston, P.A.
  • Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues
    Patent number: 6785775
    Abstract: A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from monitoring the cache memory lines which indicate invalidation of a cache memory entry because of a storage operation within backing memory. This invalidity signal is utilized to generate a doorbell type interface indication of a new application entry within the work queue.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: August 31, 2004
    Assignee: Unisys Corporation
    Inventor: Robert M. Malek