Patents Represented by Attorney, Agent or Law Firm Nelson A. Quintero
  • Patent number: 6724348
    Abstract: A laptop computer with an embedded antenna is disclosed. The laptop computer contains an LCD panel and an antenna embedded inside the LCD panel. The antenna is embedded in the gap between the covering of the LCD panel and the frame supporting the LCD on the LCD panel. The ground surface of the antenna is effectively extended through incorporating the conducting surface on the back of the LCD. When the LCD panel is opened the antenna is at a distance above the operating surface of the laptop computer and produces omni-directional radiation pattern in the horizontal plane.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: April 20, 2004
    Assignee: Wistron NeWeb Corporation
    Inventor: Chien-Hsing Fang
  • Patent number: 6719591
    Abstract: The present invention discloses a SATA interface relay connector, comprising a signal section and a power supply section that comply with the SATA interface pin assignment on one side, and one side of the signal section is coupled to a signal cable and a signal connector is disposed at the end, and the other side of the power supply section is coupled to at least one power input connector. The relay connector further couples to the rear panel of an external frame to constitute a high-speed transmission mobile rack together with the enclosure.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: April 13, 2004
    Inventor: Cheng Chun Chang
  • Patent number: 6720219
    Abstract: A split gate flash memory. A drain is disposed in the bottom of a trench formed in a substrate. A source is disposed in the substrate outside the trench. A striped floating gate is disposed at a sidewall of the trench, wherein one side of the striped floating gate is near the bottom of the trench, and the other side of the striped floating gate protrudes above the substrate. A control gate winds along the floating gate, wherein one side of the control gate is near the bottom of the trench, and the other side of the control gate in outside the trench. A metal bit line connects to the drain.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: April 13, 2004
    Assignee: Nanya Technology Corporation
    Inventor: Tsai-Yu Huang
  • Patent number: 6720820
    Abstract: A block parallel efuse apparatus blown with serial data input. The block parallel apparatus includes a high voltage source, efuse circuits, a plurality of multiplex, registers, and an input-output terminal, wherein each efuse circuit includes an efuse, a blown-control terminal, an input terminal, and an output terminal. Each efuse is coupled between the high voltage source and the output terminal of the efuse circuit.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: April 13, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Yu Meng Chuang, Mang-Shiang Wang
  • Patent number: 6716757
    Abstract: A method for forming bottle trenches. The method comprises providing a substrate formed with a pad stack layer on the top, and a deep trench with protective layer on the upper portions of sidewalls thereof, implanting ions into the lower portions of sidewalls and bottom of the trench not covered by the protective layer to amorphize the atomic structure of the sidewalls and bottom, oxidizing the amorphous sidewalls and bottom of the trench to form a bottle-shaped oxide layer thereon, and removing the bottle-shaped oxide layer.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: April 6, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Shian-Jyh Lin, Chao-Sung Lai
  • Patent number: 6713697
    Abstract: A dust and moisture free switch includes a hollow casing, a contact pole device, a control plate and an isolation part. The contact pole device is inserted to the bottom of the casing with a stationary pole and a support pole being inserted into and locating at a respective pole hole and an arc pole being attached to the top of the support pole such that the arc pole can swing leftward and rightward. The control plate is joined to the upper portion of the casing and has the bottom thereof being arranged with a central hollow post to fit with an extensible stir lever, which has a bottom thereof contacting with the arc pole. The isolation part is made of soft high molecular plastic material and passed through by and fitting with the stir lever so as to be located at and closely joined to the inner wall of the casing to perform a function of blocking dust or moisture to enter the bottom of the casing.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: March 30, 2004
    Assignee: Solteam Electronics Co., Ltd.
    Inventors: Chih Song Liu, Jui Jung Chiu
  • Patent number: 6714404
    Abstract: A stand with infrared emission, which is connected to a related circuit of a keyboard, includes a pivot seat, a base, a support plate and a gyratory arm. The pivot seat is a joining part with an end thereof being connected to the keyboard and the other end thereof having a first pivot device. The base at the lower end thereof is connected to the pivot device. The support plate has the lower side thereof integrally connecting with the upper end of the base and the upper side thereof being provided with a connection part. The gyratory arm at the lower end thereof joining the connection part of the support plate and the upper end thereof is provided with an abrupt emission seat. An infrared emitter is disposed in the emission seat and electrically connected to the keyboard. A personal digital assistant (PDA) can be placed on both the base and the support plate with the gyratory arm being adjustably rotated such that the emission seat can align with an infrared receiver so as to facilitate data transmission.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: March 30, 2004
    Assignee: Hann Hwa Industrial Co., Ltd.
    Inventor: Jorson Wu
  • Patent number: 6713349
    Abstract: A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: March 30, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Chi-Hui Lin, Chung-Lin Huang
  • Patent number: 6706587
    Abstract: Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: March 16, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Tzu-Ching Tsai, Hui Min Mao, Ying Huan Chuang
  • Patent number: 6702499
    Abstract: A pen cap is constructed to include a cap body with a clip, a lighting circuit assembly, the lighting circuit assembly including a battery set mounted inside the cap body, an IC chip mounted on the clip and electrically connected to the battery set through a switch at the top of the cap body, and LED chips of different colors electrically connected to the IC chip, and a show plate fixedly mounted on the IC chip to hold the LED chips, the show plate having a design surrounded by the LED chips.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: March 9, 2004
    Inventor: Te Hsiang Fang
  • Patent number: 6699754
    Abstract: A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 2, 2004
    Assignee: Nanya Technology Corporation
    Inventor: Yung-Meng Huang
  • Patent number: 6696325
    Abstract: A method of transferring a thin film device onto a plastic sheet. A silver-containing buffer layer is formed on a glass substrate. A transferred layer including a thin film device is formed on part of the silver-containing buffer layer. At least one first hole penetrates the transferred layer and an edge of the silver-containing buffer layer is exposed. A first plastic layer including at least one second hole is adhered to the transferred layer with a removable glue, wherein the second hole corresponds to the first hole, and part of the first plastic layer is located above the edge of the silver-containing buffer layer. The silver-containing buffer layer is oxidized to expand, thereby separating the silver-containing buffer layer from the transferred layer. A second plastic layer is adhered to the transferred layer. The removable glue is eliminated to remove the first plastic layer.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: February 24, 2004
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Yaw-Ming Tsai, Chun Hsiang Fang, Cheng-Hsun Tsai
  • Patent number: 6696344
    Abstract: A method for forming a bottle-shaped trench. A semiconductor substrate having a pad stack layer thereon and a trench in a predetermined position is provided. A first dielectric layer is then formed on the lower sidewalls of the trench. Next, a second dielectric layer is formed to cover the upper sidewalls of the trench and the pad stack layer. Then, a protection layer is formed on the sidewalls portions of the second dielectric layer. The first dielectric layer is then removed to expose the lower portion of trench. Wet stripping is then carried out to increase the radius of the lower portion of the trench thereby forming a bottle-shaped trench.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: February 24, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Shian-Jyh Lin, Hsin-Jung Ho, Chao-Sung Lai, Tzu-Ching Tsai
  • Patent number: 6695455
    Abstract: A process for fabricating micro-mirrors on a silicon substrate is disclosed, which can markedly improve the flatness of micro-mirrors, reduce the scattering of incident light, and increase S/N ratio. The fabrication process comprises the steps of: forming micro-planes along a certain direction on a silicon substrate to serve as mirrors; forming a SiO2 layer on the silicon substrate; and melting the SiO2 layer on the micro-planes by a heating process and then crystallizing SiO2 again to form micro-mirrors. Further, instead of coating the SiO2 layer, a metal layer can be used to form a eutectic structure with the silicon substrate. After the micro-mirrors are formed, a layer of Au can be coated thereon to increase the reflectance of the micro-mirrors.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: February 24, 2004
    Assignee: Industrial Technology Research Institute
    Inventor: Jung-Chieh Su
  • Patent number: 6693834
    Abstract: A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line contacts in the memory regions simultaneously. The memory deices and test may have the same alignment shift between bit line contacts and bit line due to use of the same masks and process. Thus, alignment of bit lines and bit line contacts in the memory region is determined according to two resistances (R1 and R2) detected by the test device.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: February 17, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Yu-Wei Ting, Bo Ching Jiang
  • Patent number: 6693006
    Abstract: A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 17, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Hsin-Jung Ho, Chang Rong Wu, Yi-Nan Chen, Tung-Wang Huang
  • Patent number: 6670246
    Abstract: A method for forming a vertical nitride read-only memory cell. First, a substrate having at least one trench is provided. Next, a masking layer is formed over the sidewall of the trench. Next, ion implantation is performed on the substrate to respectively form doping areas in the substrate near its surface and the bottom of the substrate trench to serve as bit lines. Next, bit line oxides are formed over each of the doping areas and an oxide layer is formed overlying the mask layer by thermal oxidation. Finally, a conductive layer is formed overlying the bit line oxides and fills in the trench to serve as a word line.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: December 30, 2003
    Assignee: Nanya Technology Corporation
    Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang
  • Patent number: D484471
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: December 30, 2003
    Assignee: Benq Corporation
    Inventors: Chia-Chuan Lin, Yung-Chuan Ma, Chien-Jui Wang
  • Patent number: D485273
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: January 13, 2004
    Assignee: Benq Corporation
    Inventors: Shu-Fen Ke, Wen-Ming Wu, Chun-Hsiung Yin, Chien-Jui Wang
  • Patent number: D487260
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: March 2, 2004
    Assignee: BENQ Corporation
    Inventor: Liang Wang