Abstract: A method to perform image transformations that are simplistic, conducive to miniaturization, and inexpensive to implement is provided. Transformations of an image stored in system memory are carried out by copying the image data, transforming the image data to a selected orientation, and outputting the transformed image for display, printing, or others. Throughout the transformation process, the image stored in system memory remains unchanged in the original orientation (T0-normal transformation). The transformation process is carried out by accessing in predetermined orders/sequences the image data copied from system memory to a frame buffer that is made up of N memory modules and arranged such that image data are stored serially with the image scan lines running the length of the frame buffer like that of a traditional frame buffer but with each memory module capable of being individually accessed.

Abstract: An apparatus to power up an integrated device from a low power state wherein the clock circuit for generating the internal clocks has been disabled is provided. A small set of programmable registers is reserved inside the CPU interface unit (CIF) of an integrated device (e.g., a display/graphics controller) which can be accessed by the CPU even during a low power state mode (e.g., software controlled sleep mode D3 in the preferred embodiment). The programmable registers store programmed bits that are used in indicating to the Power Management Unit (PMU) the desired power state and whether the clock circuits are to be enabled or disabled. The programmable registers also store multiplication and division factors to be used by the clock circuits in determining their clock rate. Using this information, the integrated device can go through a predetermined power sequence to transition from the low power state to the normal state which includes powering up the clock circuits (e.g., PLLs and oscillator).

Abstract: A high-resolution digital image capturing apparatus with variable resolution capability is presented. In accordance with the present invention, the image capturing apparatus implements a motion control mechanism to incrementally move the sensor array relative to a subject. A frame of the image is captured at each incremental position. The number of frames taken is essentially limited by the distance between adjacent sensors. The frames are subsequently processed and assembled to generate a picture with improved resolution. Accordingly, the image resolution is directly related to the number of frames taken. By using the concept of fractal geometry, the number of frames required for high image resolution may be reduced thereby essentially providing a compressing technique to reduce capturing and processing time. In so doing, a digital image capturing apparatus with variable resolution capability that is inexpensive, portable, and power efficient can be achieved.

Abstract: A modular offset Automated Testing Equipment (ATE) test head with split backplane is presented. The ATE test head is modularized into a card cage module having a first backplane for accommodating general purpose instrument cards and a cassette module having a second backplane that is offset relative to the first backplane for accommodating personality (specific purpose) instrument cards. The general purpose instrument cards and the personality instrument cards communicates with each other by cables connecting them. The general purpose instrument cards and personality instrument cards can be quickly disengaged from and engaged to the respective backplanes individually or concurrently. Because of this latter feature, a cassette module can be easily and rapidly disengaged from the card cage module and a different cassette module can be easily and rapidly engaged to the card cage module.

Abstract: An automatic Engineering Change Order (ECO) methodology to effectively and efficiently carry out an ECO process is provided. In the present invention, an ECO framework, which includes a database and Computer Aided Design (CAD) software tools, is implemented as part of the ECO process. The ECO framework database is used in monitoring the gate array cells reserved for ECO modifications. In addition, the database also stores information related to the gate array cells such as their timing characterization, fanout characteristics, physical locations, and others. The database also includes library for storing selected connectivity patterns for logic cells. On the other hand, the ECO framework CAD software tools are used to place the reserved gate array cells in a physical layout and to monitor their status. The CAD software tools is also used to select gate array cells from the database for ECO changes according to predetermined criteria.

Abstract: A Graphics Engine (GE) FIFO interface architecture that allows the transfers of reduced address information from the GE to the frame buffer is provided. The FIFO interface architecture further allows the GE to be isolated from the Memory Interface Unit (MIU) or the Central Processor Interface Unit (CIF) such that the GE can operate at a different frequency from the MIU and the CPU. Address information is provided using two flag bits End of Line (EOL) and Add One (AO). In write mode, flag bits EOL and AO are used to determine the next address in the frame buffer where processed data from the GE is to be stored. In line draw mode, flag bits EOL and AO are used to determine the address in the frame buffer for data retrieval. Such data retrieval allows a rendered line to perform background and foreground color ROP in line draw commands. Flag bit EOL indicates whether the GE needs to skip to the next scan line (e.g., the end of the current scan line has been reached).

Abstract: An apparatus that allows for high capacity and fast access command queuing without requiring excess host processor overhead clock gating apparatus that is cost efficient and allows power conservation is provided. A command and its associated data to be processed by a graphics engine are formatted as data structures and first stored in system memory. A number of these data structures can be queued in system memory at any given time. Each data structure includes a header that provides information related to the data words in the data structure such as the number of the data words involved, their destination address, and others. Using the header information provided, the command and its associated data are sequentially provided to the graphics engine for processing.

Abstract: A dynamic, efficient, and full-duplex wireless local network is presented. The local central station equipment is implemented by implementing a Frequency Division Multiple Access (FDMA) technique on local inbound data and a Time Division Multiple Access (TDMA) technique on at least local outbound data. Conversely, each subscriber unit implements the TDMA technique on local outbound data and the FDMA technique on local inbound data. In so doing, wireless two-way communications can be established between the central station, subscriber units, and remote stations wherein the allocated carrier frequency band is fully utilized and the outbound data bandwidth can be dynamically adjusted to accommodate the bandwidth requirements of different communication applications.

Abstract: A programmable Power Management Unit (PMU) is provided. The Power Management Unit (PMU) supports a number of different power states namely a normal power state, a software-controlled sleep power sate, a hardware-controlled sleep power state, and two register programmable power states. In the normal power state, all circuits in the integrated circuit (e.g., graphics/display controller) are enabled. In the software-controlled sleep power state, all circuits in the integrated circuit are disabled except for frame buffer memory refresh logic and part of the bus interface. In the hardware-controlled sleep power state, all circuits in the integrated circuit are disabled except for the memory interface logic. In the two register programmable power states, circuits can be selectively powered up or down as desired in a single power sequencing. Moreover, under the present invention, the interval between circuits that are being disabled or enabled in a power sequencing is also programmable.

Abstract: A apparatus to generate gray scale shading data in response to input color data that is cost efficient and programmable is presented. The present invention allows up to 16 brightness-levels to be generated per color (e.g., Red, Green, and Blue). Under the present invention, each color pixel can be programmed to have one of the 16 brightness-level waveforms stored in a memory by dynamically changing a number of variables such as pixel color offsets, frame offset, column offset, row offset, pixel mapping data, etc. An accessing waveform index is generated from the above variables which is then used to select a brightness-level waveform from the memory. The brightness-level waveforms stored in the memory are also programmable.

Abstract: A clock gating apparatus that is cost efficient and allows power conservation is presented. The clock gating apparatus is implemented to allow data paths, that are used to process data, to be enabled or disabled as desired while preventing the clock-skew problem. The clock gating apparatus includes a plurality of clock gating circuits, wherein one clock gating circuit is implemented for each data path. In a first embodiment, while all the data paths propagate data in a first direction and eventually merge together at a node, the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction. In a second embodiment, parallel data paths that are mutually exclusive of each other propagate data in a first direction and the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction.