Abstract: A new and improved voltage multiplier circuit is provided which converts a relatively low voltage to a relatively high voltage without any undesirable voltage drops across any of the constituent components. A plurality of the disclosed voltage multiplier circuits may be cascaded together to increase the multiplied output voltage, wherein each multiplier stage of the cascaded circuits multiplies the input voltage by two.

Abstract: An RF oscillator and modulator produces a stable moudlated RF signal with a varying voltage source and without the requirement for critical device selection. A bias voltage for the oscillator transistor is provided by diode means at the oscillator output, the bias voltage being commuted to the transistor through the oscillator tuned circuit. Advantageously, the diode means biases a diode modulator connected to the oscillator output and to a modulation signal whereby linear operation of the diode modulator is enhanced.

Abstract: A very high-speed exclusive OR/NOR circuit in which output function and its complement are propagated simultaneously. Developed particularly for use in integrated circuit applications, the basis circuit uses six NPN transistors in a tree configuration to select one of four mutually exclusive conductive paths which correspond to the four states of the truth table of a two-variable exclusive OR/NOR function.

Abstract: An AC to DC voltage converter provides both regulated and unregulated voltage from the positive DC voltage output terminal which is connected to a power input terminal of a load. One load circuit is returned to a common circuit terminal (e.g. ground) and another load circuit is returned to the converter whereby the regulator is by-passed.

Abstract: A memory cell is provided which comprises a word line, a current source line, a pair of bit lines, a first transistor having a base terminal, a collector terminal coupled to the word line, a first emitter coupled to a first of the pair of bit lines, a second emitter coupled to the current source line, a second transistor having a base terminal coupled to the collector terminal of the first transistor, a collector terminal coupled to the word line and to the base of the first transistor, a first emitter coupled to a second of the pair of bit lines, and a second emitter coupled to the current source line, and means for directing more current through the second transistor than through the first transistor.

Abstract: A device for introducing a known amount of charge to a line of charge storage elements in a charge-coupled device fabricated in a conductor-insulator-semiconductor system includes a buffer charge storage element fabricated adjacent a first charge storage element in the line of charge storage elements, the buffer charge storage element having its gate electrode controlled by a logic pulse whose level determines whether charge is to be introduced to the line of charge storage elements, and precharge means coupled to this buffer charge storage element for supplying a saturating charge to the buffer charge storage element.

Abstract: An improved memory cell comprising a word line, a pair of bit lines, a pair of load impedances, and a pair of switching transistors. The pair of switching transistors each include an emitter coupled to a respective one of the bit lines, a base coupled to a respective one of the load impedances, and a collector coupled to the base of the other switching transistor. The pair of load impedances may include a pair of transistors each having an emitter coupled to the word line, a base coupled to a respective one of the emitters of the pair of switching transistors, and a collector coupled to a respective one of the bases of the switching transistors.

Abstract: An improved method of MOS circuit fabrication includes the consecutive steps of formation of a selected material on the surface of an underlying substrate, removal of the selected material from selected portions of the underlying substrate, and formation of insulating material between the selected material and the underlying substrate on the surface of the newly exposed underlying substrate.

Abstract: A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Q.sub.ss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.

Abstract: A process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases in a semiconductor substrate utilizes the stopping power of different layers of materials to determine the location of impurity concentrations induced by ion implantation.

Abstract: A line-addressable random-access memory (LARAM) comprises a plurality of lines of charge storage elements, means for introducing charge representing binary information to the beginning of particular ones of the plurality of lines of charge storage elements which are addressed, at least one data clock signal means for effecting the transfer of charge along those lines of the charge storage elements which are addressed, an address-selection matrix electrically coupled between the clock signal means and the lines to permit the addressed ones of the lines to be clocked, and charge-sensor means for receiving charge from the addressed lines and, in response thereto, generating a signal which represents the data signified by the charge and for recirculating a refreshed representation of the charge to the means for introducing charge.

Abstract: A phase-locked loop frequency synthesizer is described not having the uncontrolled modulation of its output normally associated with such a synthesizer due to a detection dead band inherent in the phase/frequency comparator which is a principal part thereof. The frequency synthesizer includes, as is conventional, a reference oscillator and an oscillator for generating the synthesizer output. The comparator is also included as is conventional to detect unwanted deviations of the phase and frequency of the synthesizer output so they can be corrected. In order to compensate for the inability of the comparator to detect small unwanted deviations, a pulse generator is added to the synthesizer to apply what is, in effect, an intentional periodic phase error signal greater than the dead band difference. This causes the phase of the desired output to be corrected in a controlled manner which will prevent undesired frequency modulation of its output.

Abstract: A new and improved memory cell is provided which comprises a word line, a pair of bit lines, a pair of current sources each having a first side coupled to a corresponding one of the bit lines; and a bistable circuit means operatively coupled to the word line and to another side of each of the current sources, whereby the bistable circuit means assumes one stable state upon the application of a voltage on one bit line, and assumes another stable state upon the application of a voltage on the other bit line.In addition, several embodiments of semiconductor structures are provided for the new and improved memory cell.

Abstract: An analog-to-digital converter of the single slope detection type comprising a first input terminal for receiving a first input signal formed by the superposition of a common mode noise voltage on a first DC voltage, a second input terminal for receiving a second input signal formed by the superposition of the common mode noise voltage on a second DC voltage, a ramp generator responsive to the second input signal and operative to separate the common mode noise voltage from the second input signal and to develop a ramp reference signal that is modulated by the common mode noise voltage, a first comparator for comparing the signals at the first terminal and at the output of the ramp generator and for developing a first output signal which changes state when the level of the modulated ramp reference signal exceeds the level of the first input signal, a second comparator for comparing the signals at the second terminal and at the output of the ramp generator and for developing a second output signal which changes

Abstract: A monostable multivibrator has improved output control by minimizing the recovery time of a transistor pair and using a voltage comparator for comparing the recharging voltage of the timing network with a reference for output signal development. Recovery time is minimized by employing a Darlington circuit for accelerating discharge of the timing network in response to the trigger signal to the monostable transistor pair, whereby the voltage comparator generates an output signal which is a function primarily of recharging time of the timing network.

Abstract: A high-voltage transient protection circuit for use in combination with a voltage regulator of the type employing an error amplifier to compare a portion of the controlled output voltage against a reference voltage and adjust the output voltage accordingly. The protection circuit can be used with three terminal positive or negative voltage regulators of either the shunt transistor or series pass transistor types. Oscillation of the protection circuit around a selected transient voltage threshold is avoided by providing a hysteresis characteristic in the response of the circuit to a voltage transient. The circuit is preferably embodied as an integrated circuit in a chip of semiconductor material and is particularly well suited for protecting a voltage regulator and associated electronic systems from the detrimental voltage transients encountered in an automotive environment.

Abstract: A self-aligned charge coupled device comprises a semiconductor substrate having implanted barrier regions, an insulation layer disposed over the substrate, a first layer of closely spaced electrodes, a second layer of closely spaced electrodes interlaced between electrodes of the first layer and separated by insulation, and a conductor deposited between the first and second electrodes so as to electrically connect portions of the first electrodes to portions of the second electrodes.