Abstract: This invention is a method of forming a nitride layer on at least one metal or metal alloy biomedical device, comprising: providing a vacuum chamber with at least one biomedical device positioned thereon on a worktable within the vacuum chamber; reducing the pressure in the vacuum chamber; introducing nitrogen into the vacuum chamber so that the pressure in the vacuum chamber is about 0.01 to about 10 milli-Torr; generating electrons within the vacuum chamber to form positively charged nitrogen ions; providing a negative bias to the worktable so that the positively charged nitrogen ions contact the biomedical devices under conditions such that a nitride layer forms on the at least one prosthetic device.

Abstract: The present invention relates generally to the preparation and use of biological tissue adhesives which rely on combining fibrinogen and thrombin. More particularly, the present invention relates to a method of preparing a fibrin sealant whereby said sealant is formed by reconstituting the fibrinogen or the thrombin component in the presence of biological and/or non-biological agents such as drugs, chemicals, and proteins. Preferably, these agents are introduced in solution, such as for example, a corticosteroid-containing solution like a betamethasone solution containing betamethasone acetate or betamethasone sodium phosphate; a triamicinolone solution; or a methylprednisolone solution. These solutions may be substituted for, or provided as a complement to, other solutions that are typically used in the preparation of fibrin sealants such as, for example, calcium chloride.

Abstract: A programmable logic device (PLD) includes programmable electronic circuitry. The programmable electronic circuitry allows programming the functionality of the PLD. The programmable electronic circuitry includes one or more of programmable interconnects, pass devices, look-up table circuits, and/or multi-input logic circuits. Each of the programmable interconnects, pass devices, look-up table circuits, and/or multi-input logic circuits includes one or more of dynamic threshold metal oxide semiconductor (DTMOS) transistors, fully depleted metal oxide semiconductor (FDMOS) transistors, partially depleted metal oxide semiconductor (PDMOS) transistors, and/or double-gate metal oxide semiconductor transistors.

Abstract: Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

Abstract: Cement compositions for cementing wellbores in cold environments. The cement compositions may include a mixture of a reactive aluminum silicate, aluminum sulfate and hydraulic cement, and may include one or more other additives. The cement compositions may be formulated to have reduced heat of hydration as compared to conventional cements, making them suited for cementing in permafrost environments. The cement slurries may optionally be foamed using a foaming agent and energizing phase.

Abstract: A precision timing generator includes a combiner that provides a timing signal by combining a coarse timing signal and a fine timing signal derived from a phase-shifted sinusoidal signal that has a desired phase shift. The coarse timing generator generates the coarse timing signal from a clock signal and a timing command input. The fine timing generator includes a sinusoidal-signal generator that receives the clock signal and generates a sinusoidal signal. The fine timing generator also includes a phase shifter that receives the sinusoidal signal and the timing command input and shifts the phase of the sinusoidal signal based on the timing input to generate the phase shifted sinusoidal signal.

Abstract: This invention concerns a method for the preparation of polyurea elastomers, comprising: (a) reacting an amine chain extender with dialkyl maleate to form an aspartic ester, wherein the chain extender has a molar amount of amine groups that is greater than the moles of dialkyl maleate; (b) blending the aspartic ester with one or more polyoxyalkyleneamines to prepare a resin blend; (c) contacting the resin blend with an isocyanate under conditions effective to form a polyurea elastomer. This invention concerns a method for the preparation of polyurethane elastomers, comprising: (a) reacting an diamine chain extender with dialkyl maleate or fumarate, wherein the mole ratio of primary amine functionality in the diamine chain extender to dialkyl maleate or fumarate is more than 1:1; (b) coating a substrate with effective film forming amounts of the product of step (a), an isocyanate, and a polyhydroxyl compound under conditions effective to form a the polyurethane elastomer.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a more general terms, a frequency synthesizer is disclosed having a first variable and a second capacitance circuits and frequency control circuitry to coarsely tune the output frequency by adjusting the first control signal and to finely tune the output frequency by adjusting the second control signal.

Abstract: Methods and compositions for stimulating multiple intervals in wells by diverting well treatment fluids into multiple intervals by alternately displacing diverting agent from the annulus into a subterranean formation and displacing treatment fluid from a tubing string into the subterranean formation.

Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.

Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance.

Abstract: A method and apparatus are provided for suspending or freezing outputs from an isolation barrier system, which may be a digital capacitive isolation barrier system, during the occurrence of events that may disrupt proper operation of the system. Examples of such disruptive events are data rate changes during modem baud rate negotiations, transition to low-power mode, and going off-hook in a telephony system. In each of these cases, the master circuit anticipates the disruption and sends a freeze signal to the isolated circuit. The freeze signal instructs the isolated circuit to enter freeze mode, and no data is sent through the isolation system. Internal control signals are generated and used to establish synchronization and framing after the disruption, and to restore normal operation of the isolation system. In preferred embodiments, the duration of the freeze period may be determined by a timer or by circuitry that detects framing lock or the presence of transients in the system.

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock.

Abstract: An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while allowing control of modem processing so that it may be bypassed if raw data, such as raw pulse-code-modulated (PCM) data, is desired to be transmitted or received.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, wireless communication frequency synthesizer for generating multiple band high-frequency signals is disclosed having a first VCO selectable for a first frequency band and a second VCO selectable for a second frequency band.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. The offset calibration system includes a coarse offset signal generator which provides ;elected increments of offset voltage to the ADC outside of the outgoing data signal channel, In order to increase the calibration range and to avoid injecting large offset voltages into the outgoing data channel. Fixed bias signals are also provided for the ADC and for a DAC in the system.