Abstract: Systems and methods for providing a weighted overlap and add (WOLA) architecture and/or for providing polyphase WOLA FFT processing that may be employed, for example, for separation or channelization of closely-spaced frequencies of an input signal. A WOLA architecture that may be implemented as first-in-first-out (FIFO) cores in an FPGA or ASIC device. The FIFO cores may be pre-existing (e.g., provided as free FIFO cores in a commercial off the shelf (COTS) FPGA device) or may be custom-programmed into a custom ASIC device.

Abstract: An optical spectroscopy tool is provided. In one embodiment a highly efficient means by which moderate resolution spectroscopy may be performed in the vacuum ultraviolet (VUV) is described. In one embodiment the techniques can be used as a high throughput spectrometer to spatially disperse wavelengths in and around the VUV in such a manner as to generate a substantially flat field focal plane, suitable for use in combination with an array detector. Some embodiments utilize prism based spectrometers. Some embodiments utilize detector elements that may be movable and/or located within the spectrometer. In some embodiments, collimated light may be provided as an input to the spectrometer.

Abstract: Network communications in physical layer frame-based networks may be authenticated based on inter-packet gap (IPG) characteristics such as inter-packet gap length, inter-packet gap length pattern, information contained in the inter-packet gap, etc.

Abstract: Systems and methods are disclosed for forming reconfigurable neural networks with interconnected FPGAs each having a packet router. Neural network nodes are formed within the FPGAs and connections between nodes within an FPGA and connections to nodes external to the FPGA are made using packet routers that are configured within each FPGA. The FPGAs can be connected to each other using high-speed interconnects, such as high-speed serial digital interconnects. The FPGA arrays with packet routing allow for dynamic and reconfigurable neural networks to be formed thereby greatly improving the performance and intelligence of the neural network.

Abstract: Systems and methods for distribution of wireless network access using a common media access control (MAC) architecture. In one embodiment, a platform architecture may be provided for high speed Broadband Wireless Access (BWA) service termination using a common MAC architecture and router functionality, e.g., an integrated router and firewall service may be provided to a local WLAN network, leveraging a common orthogonal frequency division multiplexing (OFDM)-based MAC architecture for both the BWA and WLAN functionality. Such a common MAC architecture may be implemented to optimize the performance and throughput between the broadband wireless ISP data service and localized WLAN network.

Abstract: Systems and methods for evaluating electromagnetic interference that may be employed, for among other things, to evaluate electronic system immunity to radiated electromagnetic fields and/or to identify particular electronic system areas that are susceptible to electromagnetic radiation.

Abstract: An adaptive channel equalization technique and method for wideband passive receivers is disclosed that reduces and tends to minimize distortions caused by circuitry within passive digital receivers. This equalization architecture provides an adaptive equalization solution for a wideband passive channel that receives unknown signals from the RF environment both temporally and spectrally. A wideband chirp signal or calibration signal is periodically injected to capture the spectral response of the receiver channel as it varies from the distortions induced over time and temperature for synthesis of equalization filter coefficients. Thus, the channel equalization is performed independent of receiver signal source and is employed to minimize digital receiver signal measurement distortions across the passband by providing an equalization filter whose magnitude and phase response compensates for the channel distortions of the passive data collection system.

Abstract: Test data model and test data structure creation improvements are disclosed for enterprise test data management systems in the test, measurement and automation environment. A hierarchical test data model for a plurality of test systems includes hierarchical data objects configured to store test data related information. In addition, one or more data objects within the test data model are linked such that data entered into one object can be used by another object or can be automatically propagated to linked objects. And default data object properties are defined such that each new data object includes the default properties. Still further, a graphical user interface (GUI) can be provided through which information can be input to the database where the GUI includes a first frame showing a structure for the hierarchical test data model and a second frame automatically showing one or more data input fields related to an object selected within the first frame. Related systems and methods are also disclosed.

Abstract: Systems and methods for solder bonding that employ an equilibrium solidification process in which the solder is solidified by dissolving and alloying metals that raise the melting point temperature of the solder. Two or more structure surfaces may be solder bonded, for example, by employing heating to melt the solder and holding the couple at a temperature above the initial solder melting point of the solder until interdiffusion reduces the volume fraction of liquid so as to form a solid bond between surfaces before cooling to below the initial melting point of the solder.

Abstract: A water-based lubricant composition, comprising: water, molybdenum disulfide, polytetrafluoroethylene, and a polymeric binder, wherein the binder is an acrylic resin or a polyurethane resin.

Abstract: A method and associated system are disclosed for verifying charging failures for smart batteries by measuring input charging voltage and associated systems. In one embodiment, a determination is made whether or not a charging current is indicative of a battery failure by utilizing an analog-to-digital (A/D) port to measure the input charging voltage. As long as the measured input charging voltage is below the cell pack voltage or some set voltage value, whichever is higher, the BMU considers a charging current detection to be a false failure indication. If the measured charging voltage is above the cell pack voltage and the set voltage value, the BMU considers the charging current detection to be a positive failure indication. The BMU can then disable the battery or implement other verification steps before disabling the battery, as desired.

Abstract: Methods and systems are disclosed for charge current adjustment to enhance battery cycle life thereby allowing batteries to be charged quickly without accelerating the aging process of the battery. As the charge capacity of the battery degrades over time, the charge current for the battery charging cycles is also reduced so that the effective charge rate for the battery is adjusted to account for the reduction in charge capacity. In this way, battery capacity life is enhanced by avoiding an accelerated charge rate as the battery capacity drops over the operational life of the battery. The methods and systems disclosed are useful for battery-powered information handling systems, as well as other devices where fast charging and long cycle life is desirable, such as cell phones, personal digital assistants (PDAs), electric vehicles and/or any other battery powered devices.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable circuit for the DC termination for a variety of international phone standards. The invention may also be utilized with circuitry for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: An infrared image detector system mounted on a printed circuit board (PCB) is disclosed for use with an infrared imaging system such as an infrared camera. A semiconductor die having an infrared detector array and connection points on a first surface is mounted to a PCB and electrically coupled to electrical connection points on a PCB. In addition, a heat sink can be coupled to an opposing second surface of the semiconductor die. Still further, the PCB can have a window within which the infrared image detector array can be positioned so that the infrared image detector system can be mounted to one side of the PCB while infrared radiation incident on the second side of the PCB will reach the infrared image detector array through the window.

Abstract: Systems and methods for providing a SIM module for an information handling system, such as desktop computer, notebook computer or other type of portable information handling system, etc. An information handling system may be assembled so that a SIM module need only be installed into the information handling system when SIM functionality is required to support a GSM type WWAN card, and not installed when such WWAN capability is not needed.

Abstract: A method and system are disclosed for improving the efficiency of a battery supplied power supply system. More particularly, a method and system is provided for improving the voltage regulation efficiency for a system in which the input voltage that is to be regulated may vary widely. In the techniques disclosed, the voltage supply that is utilized for the drive control circuitry of the voltage regulators is varied in relation to variations in the input voltage. Thus in one embodiment, the voltage supply that is utilized for the circuitry that drives a control terminal of the output transistor of the regulation circuitry may be varied in relation to variations in the input voltage. For example, an inverse relationship may be established between the input voltage level and the voltage level that is used for the gate drive circuitry that controls the gates of regulator output transistors.

Abstract: A reflectometer calibration technique is provided that may include the use of two calibration samples in the calibration process. Further, the technique allows for calibration even in the presence of variations between the actual and assumed properties of at least one or more of the calibration samples. In addition, the technique utilizes a ratio of the measurements from the first and second calibration samples to determine the actual properties of at least one of the calibration samples. The ratio may be a ratio of the intensity reflected from the first and second calibration samples. The samples may exhibit relatively different reflective properties at the desired wavelengths. In such a technique the reflectance data of each sample may then be considered relatively decoupled from the other and actual properties of one or more of the calibration samples may be calculated. The determined actual properties may then be utilized to assist calibration of the reflectometer.

Abstract: Systems and methods that may be implemented to determine the location of an emitter of electromagnetic radiation, such as an RF signal emitter having an unknown location, using at least two electromagnetic radiation sensor antennas that are co-located on a single sensing platform in combination with at least one other electromagnetic radiation sensor antenna located on another sensing platform.

Abstract: Systems and methods for providing access to shared storage, for example, using multiple information handling system nodes configured as server nodes. Each server node is given ownership of different portions of data on the shared storage so that each portion of data is allowed to have only one owner at any given time. Data ownership information may be globally stored and used by the multiple server nodes to determine ownership and control access to a requested portion of data.