Abstract: A semiconductor wafer having two regions of different dopant concentration profiles is evaluated by performing two (or more) measurements in the two regions, and comparing measurements from the two regions to obtain a reflectivity change measure indicative of a difference in reflectivity between the two regions. Analyzing the reflectivity change measure yields one or more properties of one of the regions if corresponding properties of the other region are known. For example, if one of the two regions is doped and the other region is undoped (e.g. source/drain and channel regions of a transistor), then a change in reflectivity between the two regions can yield one or more of the following properties in the doped region: (1) doping concentration, (2) junction or profile depth, and (3) abruptness (i.e. slope) of a profile of dopant concentration at the junction. In some embodiments, the just-described measurements in the two regions are performed by use of only one beam of electromagnetic radiation.

Abstract: Adding a layer of abstraction to the generation of a runset for DRC rules, by defining a meta language hides from the user the language of a specific verification tool (also called “native language”). The meta language can be used directly by the user to express in a file (also called “meta runset”) the DRC rules to be used to create an input for the verification tool in the native language (also called simply “runset”). A runset generator uses DRC rules supplied by a user to generate a runset in a native language (that is identified by the user). The runset generator can use templates to generate a runset. Each template (also called “DRC template”) contains code (can be in source form or in object form) for implementation of a DRC rule or derived layer in the native language of a specific verification tool (such as HERCULES). Thus implementation of DRC rules is hidden from the novice user.

Abstract: In simulating a physical circuit or system including analog and mixed signal digital-analog components, a physical circuit or system includes components defined as instances of models. There can be multiple instances of any model in the physical circuit or system. For each model, a sub-system of simultaneous equations is determined. The variables in the sub-systems of simultaneous equations are classified as input, output, intermediate, or system variables. Equations are associated with each variable, and the sub-systems of simultaneous equations are reduced by eliminating all equations not associated with system variables. The system of simultaneous equations describing the physical circuit or system is assembled from the sub-systems of simultaneous equations. For each instance of a model, a copy of the sub-system of simultaneous equations for that model is added to the system of simultaneous equations.

Abstract: Different frames received on a first port are processed by different processing channels in parallel. The processed frames are transmitted to a second port in the same order in which they were received on the first port. The ordering is maintained using a FIFO that receives the number of a processing channel whenever a frame is dispatched to the processing channel. The processing channels are selected to provide frames to the second port in the order of the channel numbers in the ordering FIFO.

Abstract: A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit. The error correction process corrects single bit hard errors in a stored digital data word of “n” bits according to the following steps. The process generates a parity bit for the n-bit word according to a predetermined algorithm prior to storing the word. The process then stores the digital data word in a selected storage location and also stores the parity bit. The process retrieves the stored n-bit word from the selected storage location. The process also retrieves the stored parity bit for the n-bit word. Then, the process generates a new parity bit for the retrieved word according to the predetermined algorithm. The new parity bit is compared with the retrieved parity bit.

Abstract: A memory controller configured according to a delay pair for communicating with a memory device automatically selects optimal delay pairs by testing whether successful communication exists at various values for the delay pairs. The resulting set of delay pairs allowing successful communication are divided into a boundary set and non-boundary set. An optimal delay pair from the non-boundary set is chosen according to its relationship to delay pairs in the boundary set.

Abstract: A method (1) creates charge carriers in a concentration that changes in a periodic manner (also called “modulation”) only with respect to time, and (2) determines the number of charge carriers created in the carrier creation region by measuring an interference signal obtained by interference between a reference beam and a portion of a probe beam that is reflected by charge carriers at various depths of the semiconductor material, and comparing the measurement with corresponding values obtained by simulation (e.g. in graphs of such measurements for different junction depths). Various properties of the reflected portion of the probe beam (such as power and phase) are functions of the depth at which the reflection occurs, and can be measured to determine the depth of the junction, and the profile of active dopants.

Abstract: A circuit collects data from a number of locations in a system memory of a personal computer, and can refetch the collected data at any time, e.g. when an adapter for transferring data between a computer bus and a peripheral bus that includes the circuit encounter an unexpected event (such as an error) in the transmission (or retransmission) of data to a first peripheral device. So the adapter simply flushes the data on encountering the unexpected event. Thereafter, the adapter switches context, to transfer data to a second peripheral device. At a later time, the circuit in the adapter refetches the flushed data, for retransmission of the data to the first peripheral device. To refetch the flushed data, the circuit does not traverse backwards through a scatter/gather data transfer pointer list (described above) that is used to collect the data from system memory.

Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Abstract: A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0.

Abstract: An integrated circuit chip has pads that are grouped into a number of groups, and also has functional modules that share, among each other, use of two or more groups of the pads (also called “external function” groups), for transferring signals (such as data signals and control signals) to or from external circuitry. Each functional module has one or more groups of terminals (also called “internal function” groups) for carrying these signals. The number I of internal functional groups is greater than another number E of external function groups. Therefore, at any given time, a number I-E internal function groups are uncoupled (i.e. not coupled to any pads of the integrated circuit chip). Couplings among groups are implemented independent of each other in a crossbar switch having I internal ports and E external ports, and at least I-E internal ports are always uncoupled.

Abstract: The Model Editor (106) makes simulation modeling easier and more intuitive by extracting essential information and presenting it to the user, and by providing tools to investigate simulation and model robustness, in an interactive, graphical environment. The Model Editor (106) includes a Newton step manager as an interactive, graphical tool. During simulation of a model, the Newton step manager captures matrix norms. Any indications of Newton limiting are also captured. The matrix norms are plotted as a function of iteration count, and the iterations at which Newton limiting were encountered are identified. Newton step manager can also be run automatically using a functional dependency analysis.

Abstract: A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions.

Abstract: A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two memory portions in a data path simultaneously: one for receipt and another for transmission. Specifically, each data path uses a memory portion to hold data that is currently being received, while using another memory portion containing data that was previously received for simultaneous transmission from the host adapter. Each of the data paths transfers data in a continuous manner irrespective of the context (e.g.

Abstract: A microscope uses electrostatic force modulation microscopy to measure mechanical and electrical characteristics of a sample. A tip contacts the sample while a voltage (which may have dc and ac components) is applied between the tip and sample. The tip oscillates even though the tip is contacting the sample due to strong electrostatic force interaction between the tip and sample. Different characteristics of the sample such as hardness, surface potential, capacitance, surface charge, and so forth, are measured by manipulating the oscillation of the tip relative to the sample and monitoring the position of the tip.

Abstract: A ratiometric sensor is formed of a first photodiode connected in series with an electronic component, such as a second photodiode or a resistor, between a source of first voltage and a source of second voltage. The ratiometric sensor supplies a "ratiometric voltage" on a ratiometric sensor output line that is connected to a junction between the first photodiode and the electronic component. The ratiometric voltage is proportional to the ratio of the equivalent resistance of the first photodiode to the sum of the equivalent resistances of the first photodiode and the electronic component. A ratiometric sensor that uses a photodiode and a resistance has a large dynamic range because the ratiometric voltage can vary between the first voltage and the second voltage. A ratiometric sensor that uses two photodiodes is less sensitive to noise than a conventional circuit that uses a single photodiode, because noise can get canceled from the numerator and denominator of the ratio.