Abstract: A design verifier includes a bounded model checker, an abstractor and an unbounded model checker. The bounded model checker verifies a property to a depth K and either finds a counterexample, or generates a proof in the form of a directed acyclic graph. If no counterexample is found, the abstractor generates an abstracted design description using a proof generated by the bounded model checker. The unbounded model checker verifies the property of the abstracted design description. If a counterexample is found, the bounded model checker increases K and verifies the property to the new larger depth. If no counterexample is found, the design is verified.

Abstract: A non-uniform transmission line, including at least a first section with length L1, uniform width W1 and thickness h1, and a second section with length L2, uniform width W2 and thickness h2, joined together to form a composite structure and arranged in any of at least three distinct configurations. The composite structure (first section plus second section) may be periodic or non-periodic. Length and/or width and/or thickness of each of the two sections may be varied to provide desired values for characteristic impedance, cutoff frequency and/or time delay for signal propagation.

Abstract: A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one embodiment, the method includes building a circuit N2 that preserves a predefined specification of a circuit N1. In some embodiments, the method includes verifying that N2 and N1 indeed implement the same specification and so they are functionally equivalent.

Abstract: A method and an apparatus to improve hierarchical design implementation have been disclosed. In one embodiment, the method includes deriving boundary logic of at least one of a plurality of partitions in an integrated circuit (IC) design, marking the boundary logic of the at least one of the plurality of partitions based on at least one predetermined criterion, and performing implementation of the IC design using the marked boundary logic.

Abstract: Disclosed are novel methods and apparatus for transforming sequential logic designs into equivalent combinational logic. In an embodiment of the present invention, a design method for transforming sequential logic designs into equivalent combinational logic is disclosed. The design method includes: simulating each stage of a clocking sequence to produce simulation values; saving the simulation values; and performing a plurality of backward logic traces based on the saved simulation values to provide an equivalent combinational logic representation of a sequential logic design.