Patents Represented by Law Firm Ostrolend, Faber, Gerb & Soffen
  • Patent number: 5581100
    Abstract: A vertical trench power MOS transistor with low on-resistance is obtained by eliminating the inversion region of a conventional structure. In one embodiment, a deep-depletion region is formed between the trench gates to provide forward blocking capability. In another embodiment, forward blocking is achieved by depletion from the trench gates and a junction depletion from a P diffusion between the gates. Both embodiments are preferably fabricated in a cellular geometry. The device may also be provided in a horizontal conduction configuration in which the MOS gate is disposed on the upper surface of the semiconductor wafer over the deep-depletion region.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: December 3, 1996
    Assignee: International Rectifier Corporation
    Inventor: Janardhanan S. Ajit
  • Patent number: 5134473
    Abstract: In an image pickup system which is used on a craft flying over an object zone and comprises a first (photelectric) transducer (21) for producing a first partial (electric) signal representtive of a partial image of a partial zone lying forwardly of the craft flying at a first position and a second transducer (22) for producing a second partial signal representative of another partial image of the partial zone lying directly under the craft flying, an interval of time later, at a second position spaced from the first position by a distance between two partial zones picked up by the first and the second transducers when the craft is at the first position, a compression unit (90) compresses the first and the second partial signals into first and second compressed signals. A delay circuit (54-1) gives the first compressed signal a delay equal to the interval of time and produces a delayed signal.
    Type: Grant
    Filed: April 11, 1991
    Date of Patent: July 28, 1992
    Assignee: NEC Corporation
    Inventor: Riichi Nagura