Abstract: A controller interface for demand assigned multiple access (DAMA) devices is provided. The controller interface includes a plurality of matched pairs of receive/transmit FIFO memory devices. The receive FIFOs, controlled by a clock signal output by the DAMA devices, accept serial format data and output parallel format data onto a first parallel data bus internal to the controller interface. The transmit FIFOs, controlled by an independent clock that generates clock pulses at a rate that is approximately equivalent to that of the clock signal used to control each of the receive FIFOs, accept parallel format data from a second parallel data bus internal to the controller interface and output serial format data for ultimate use by the DAMA devices. A first buffer receives parallel format data on the first internal parallel data bus and outputs same onto a parallel control data bus external to the controller interface.