Abstract: A synchronization scheme is used in a peripheral unit controller which consists of two duplicated units whose outputs are matched. In addition, each duplicated unit contains a pair of microprocessors whose outputs are also matched. The synchronization scheme allows each microprocessor to run its own diagnostics independently, and to synchronize itself with the other microprocessor of the pair. After the synchronization occurs in both microprocessor pairs, the duplicated units are synchronized. Synchronization is achieved by using a real-time clock and the interrupt structure of each microprocessor.

Abstract: An arrangement for introducing modifications in the program of a program-controlled system. Each time a modified version of a selected program function is stored in the system, it is tagged with a function sequence number; meanwhile, the original version of the program function is retained in the system. Each time a program process is initiated, it is tagged with a process sequence number. The two types of sequence numbers are assigned from a common source. Whenever the selected program function is called by a program process, a comparison is made between the process sequence number and the function sequence number. If the comparison indicates that the process was initiated before the modification was stored in the system, the original version of the selected program function is executed; otherwise, the modified version is executed. Thus, the original version or the modified version is used consistently throughout the active life of a process.

Abstract: A detector circuit for detecting the on-hook and off-hook states of a communication line includes current and voltage sensors for generating two reference signals. One signal represents the current flowing in the line; the other represents the voltage on the line. A comparator circuit compares these two references to generate an output signal representative of the on-hook state when the magnitude of one of the references is greater than the other. When the magnitude of the one reference signal is less than the other, the comparator circuit generates another output signal representative of the off-hook state of the line. In addition, when the line is electrically isolated from ground, the two comparator output signals may drive an opto-isolator to generate two corresponding output signals electrically isolated from the comparator output signals.

Abstract: In a computer system having a cache memory and using virtual addressing, effectiveness of the cache is improved by storing a subset of the least significant real address bits obtained by translation of a previous virtual address and by using this subset in subsequent cache addressing operations. The system functions in the following manner. In order to access a memory location in either the main memory or cache memory, a processor generates and transmits virtual address bits to the memories. The virtual address bits comprise segment, page and word address bits. The word address bits do not have to be translated, but an address translation buffer (ATB) translates the segment and page address into real address bits. A subset of the least significant bits of the latter word address bits represent the address needed for accessing the cache. In order to increase cache memory performance, the cache memory comprises a cache address unit which stores the subset of the real address bits from the ATB.

Abstract: The processor's interrupt stack memory and cache memory share a common data memory and are accessed using virtual addresses. A separate address translation buffer (ATB) is used for both the interrupt stack memory and cache memory to perform the virtual address to real address translations which are required to access the common data memory. The cache ATB and a cache controller provide the addressing to access cache data words in the common memory; whereas the interrupt stack ATB alone provides the addressing necessary to access the interrupt stack data words in the common memory.

Abstract: In a telecommunications switching system having a central processor for generating control signals, peripheral units, and a power source terminal, a power control arrangement includes a plurality of power switches for selectively connecting and disconnecting the peripheral units and the power source terminal in order to minimize power consumption. Responsive to peripheral unit control signals, a power control unit, which is included in the arrangement, controls the operation of the power switches so that only those peripheral units designated by a control signal are connected to the power source terminal. After the peripheral units have been operated, the power control arrangement disconnects the operated peripheral units from the power source terminal.

Abstract: A telephone switching system is disclosed which includes a digitally controllable multifunction signaling circuit responsive to commands from a central processor to generate or to receive subscriber line pulse signals of amplitude and duration specified by the processor commands. A bridge switch amplifier arrangement having an essentially constant voltage input signal and pulse width modulated control, is used to provide a substantially constant amplitude output signal. A two-stage access switch allows the signaling circuit to be time-shared among groups of subscriber lines.

Abstract: An adder circuit for generating a completion signal indicating the completion of adder operation. A detector circuit (103) is connected to the power supply bus (102) of a multistage parallel adder for detecting voltage variations caused by the operation of the adder stages and for generating a completion signal when these voltage variations have ceased to occur for a predetermined period of time.

Abstract: A negative impedance circuit comprising a level shifter and a current mirror, includes calibration circuitry for adjusting the negative impedance to provide the precise amount of current required to compensate for current drain caused by a known impedance at varying voltage levels. A divider/multiplier circuit is connected to the line which has the known impedance and provides a signal which is directly proportional to the voltage level on the line to the level shifter which, in turn, provides a corresponding control current to the current mirror. The current mirror provides a proportional current to the line current supplied by the current mirror and may be measured at a calibration resistor and the divider multiplier circuit may be adjusted to the appropriate ratio until the exact amount of current required to offset the drain to the precision resistor is provided by the current mirror.

Abstract: Timing pulses are generated from operative synchronous data pulses by means of a crystal oscillator under direct control of the output signal of a D flip-flop. The flip-flop is set or reset depending on the phase of the clock pulse relative to the leading edge of the data pulse.

Abstract: A circuit for combining a plurality of delta modulated speech signals, each signal being represented by a stream of input bits. Once each clock cycle, a multiplexer (101) sequentially applies one bit from each of the streams to an up-down counter (103) to either increment or decrement a count contained therein. The state of the most significant bit position of the up-down counter is then stored in a D-type flip-flop (104). A feedback bit assumes the inverse state of the stored most significant bit position and is sequentially applied under the control of a binary counter (102) to the up-down counter along with a bit from each of the streams during the next clock cycle. An output bit assumes the state of the stored most significant bit position, and an output signal consisting of a plurality of output bits from successive clock cycles represents the approximate linear sum of the delta modulated speech signals.

Abstract: A detector circuit (102) is connected to the gate of a thyristor (103) for generating an output signal indicating the presence of current flowing out of the cathode of the thyristor. A switch circuit (101), which is responsive to a control signal, selectively applies the control signal in a first state to the gate and, when the control signal is in a second state, connects the detector circuit to the gate to detect current flowing out of the gate of the thyristor.

Abstract: A clock synchronization unit for controlling frequency and phase of a local clock and synchronism with an external clock signal, employs a programmable controller as a part of a phase-locked loop. The controller provides highly accurate control of the clock, including verification of the accuracy of the clock control signal before applying it to the clock oscillator as well as control of the magnitude to the clock oscillator to avoid rapid changes in frequency. In one particular embodiment, the programmable controller comprises duplicated microprocessors which perform operations in step. In a master/slave oscillator arrangement, the controller controls the slave clock oscillator as well as the master to assure tracking of the slave to the master.