Abstract: The present invention provides for a battery pack (30) comprising a housing (31) and a plurality of cells (46) within the housing (41), each cell having a positive and negative terminal. A flex circuit (48) is provided for interconnecting between the plurality of cells (46). The battery pack (30) additionally comprises biasing means (38) for providing sufficient contact pressure between the flex circuit (48) and the cell terminals.

Abstract: A communication system (10) has at least one communication resource controller (28) for allocating a limited number of communication resources among a plurality of communication units. The communication resource controller monitors the communication resources and maintains a data library of the level and duration of any interference of the communication resources. The communication units (20 and 22) are constructed and arranged to communicate information on any of the communication resources. Any one of the plurality of communication units can initiate access to a communication resource by transmitting a request therefor. In response to a proper request, the communication resource controller (28) assigns a communication resource the communication units in accordance with the data retrieved from the interference data library.

Abstract: A die pad (108) with a punched hole providing a throughway (110) is affixed upon the chip carrier base 100. Such throughway permits the electronic interconnection of the die backside (112) to a conductive runner (104) by electrically conductive material (110) set between the die backside (112) and the conductive runner (104).

Abstract: An LCD/light wedge module used in electronic equipment includes an LCD unit engaged in a central opening, which is sealed to prevent dust from entering. The light wedge module is constructed of light conducting material that is formed to direct light off a back surface and through the LCD unit to a front viewing surface to prevent hot spots.

Abstract: A circuit assembly (5) and heat spreader (12) combination comprises a first substrate (10), a power device (18) having at least one lead (22) mounted on the first substrate (10), and a second electrically insulative, thermally conductive substrate (12) mounted perpendicularly to the first substrate (10). The second substrate (12) has at least one solder receptive area (14) for solder interconnection (16) between at least one lead (22) of the power device (18) and the second substrate (12).

Abstract: A removable deformable portion 16 of a boss (12) initially fastens a first member 14 to a second member 18. Subsequent to removal of the deformable portion 16, a means (15 and 20) for alternatively fastening the first member 14 to the second member 18 fastens the first and second members.

Abstract: Briefly, according to the invention, a clip assembly 10 comprises a clip 1 and a bracket 6, each having at least one hole (4, 5, 11, and 12) for alignment with each other. Alignment of the holes is required so that a pin 13 positioned through the holes pivotally secures the bracket 6 to the clip 1. The pin has a head 15 with a diameter that is greater than at least one of the holes. The pin 13 with the head 15 is passed through the holes for retaining the clip assembly 10. In the preferred embodiment, a spring 17 is used for biasing the clip 1 towards the bracket 6.

Abstract: A snap fit contact (30) is provided for attachment to a housing (40) wall. The contact (30) includes a contact surface (31) having a peripheral depending wall (32). Snap features (34) are formed in the wall. A flange or lip (35) is carried by the wall for attachment to a flex circuit (41). The contact is received in an opening (44) in the housing. The opening includes a shoulder (47) with the snap feature engaging the shoulder.

Abstract: Briefly, according to the invention, a tilt switch 30 comprises a body 20 including a substantially conical cavity. The substantially conical cavity has at least a portion 24 which is electrically conductive. The tilt switch further has an electrical contact 32 spaced from the conductive portion 24 of the cavity. Finally, a conductive ball 34 located within the cavity selectively interconnects the electrical contact 32 and the conductive portion 24 of the cavity when the tilt switch 30 is tilted.In another aspect of the invention, a jitter switch 40 comprises a body 50 including a substantially concave shaped cavity. The substantially concave cavity has a curved bottom surface having a conductive portion (48) thereon and a sidewall having a separate conductive portion (44) thereon. A conductive ball 46 within the cavity intermittently interconnects the conductive portion of the bottom surface 48 with the conductive portion on the sidewall 44 when the jitter switch 40 is in motion.

Abstract: A BIMOS logic gate (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (36) and provides an ECL level output signal (34). A bipolar transistor (20) is biased by a complementary ECL level input signal 32'. The other portion of the differential circuit includes a bipolar transistor (30) that is biased by an ECL level input signal 32. The emitter coupled transistors 20 and 30, receiving complementary ECL level inputs, along with the MOS transistor 36, receiving MOS level inputs, combine to provide logic functions with ECL level outputs 34 and 34'.

Abstract: The initial transmission (108) from one subscriber to another subscriber is transmitted at full power. The receiving unit measures the received signal strength and returns a code (118) representing this value in a reply message (114), which is also transmitted at full power. The signal strength of the reply message is determined and may be sent to the replying subscriber unit in a subsequent transmission (122), which may now be accomplished at a reduced power level. Thereafter, both subscribers may modify their respective transmitter power levels during subsequent transmission to minimize battery consumption and maximize the operational life of the subscriber unit.

Abstract: A transceiver determines the signal quality of a desired signal and the strength of all received signals. When the signal quality of the desired signal is low, and the signal strength of all received signals is high, the receiver is adapted to operate in a higher current mode, thereby minimizing intermodulation distortion. Conversely, when the quality of the desired signal is low and the strength of all received signals is also low, or when the quality of the desired signal is above a threshold, the receiver operates in a lower current mode to conserve power and maximize battery lifetime. Also, when the transceiver adapts to operate in the higher current mode, a command is sent instructing a transmitting party to increase the quality of their message which may enable the listening transceiver to adapt (return) to a lower current mode.

Abstract: An improved mixed down synthesizer scheme 10 having a first phase locked loop 12 and a second phase locked loop 14 provides a first frequency and a second frequency respectively. The first phase locked loop 12 has at least a first programmably tunable filter 30 and a mixer 28. The second phase locked loop 14 has an output received by the mixer 28 in the first phase locked loop 12. A controlling means (18 and 20) controls the first and second frequencies and tunes the first programmably tunable filter 30. The first and the second phase locked loops 12 and 14 are programmed to maintain a constant frequency ratio between the first and second frequencies in order to maintain a minimum frequency offset from the mixed-in spurious products.

Abstract: A first conductive layer 12 is deposited on the substrate 14. Next, a second conductive layer 16 with a circuit pattern is deposited on the first layer 12. Finally, the first conductive layer 12 not residing under the second conductive layer 16 is etched off, leaving the second layer 16 above the first layer 12.

Abstract: The period of time that the squelch circuit maintains a radio receiver's audio amplifier active after the signal strength of a received carrier fades below a threshold level is inversely proportional to the strength of the received carrier immediately before the fade. This threshold level is also variable. If, immediately before the fade, the received signal strength exceeds a predetermined trigger level (Vtrg) the threshold level is raised. A buffer amplifier (102) charges a capacitor (C) to a voltage which is proportional to the strength of a received carrier. If the carrier fades below a threshold (Vth2 or Vth3, the buffer is disabled and the capacitor slowly discharges through a resistor (R). When the voltage at the capacitor crosses a reference voltage (Vref1) the output of a comparator (104) switches, thereby deactivating the receiver's audio amplifier.

Abstract: A pad grid array comprises an array of cavities (12) formed in a circuit carrying substrate (10) that are metallized (18, 20, and 22) to provide electrical conductivity. The metallized cavities are preferably hemispherical in shape and approximately the size of the solder bumps (30) coupled to a solder bumped chip carrier (28) that will be mounted thereon. Flux (26) is applied to each of the metallized cavities before positioning the solder bumped chip (28) carrier over the pad grid array. Proper mounting can be detected by tactile sensing in either human or robotic assemblers when the solder bumps "drop" into the metallized cavities.

Abstract: A BIMOS lever convertor (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (32) and provides an ECL level output signal (34). The other portion of the differential circuit includes a bipolar transistor (18) that is biased by the MOS transistor (16). The bipolar transistor (18) operates to provide a complementary ECL level output signal (34') so as to provide a single ended MOS to differential ECL interface suitable for integration in an I.C.