Abstract: A multi-phase power switching converter having first and second states includes a pulse width modulator having an output, a converter output providing an output signal, and a plurality of drivers, each having an output electrically coupled to the converter output and an input. When the converter is in the first state where a duty cycle of the converter is less than or equal to 100 divided by the number of drivers, each of the driver inputs is configured to be sequentially electrically coupled to the pulse width modulator output. When the converter is in the second state where the duty cycle of the converter is greater than 100 divided by the number of drivers, each of the driver inputs is simultaneously electrically coupled to the pulse width modulator output.

Abstract: A phase-locked loop includes a sample selector configured to select a set of samples from an oversampled portion of a data signal, a dynamic phase decision control circuit configured to indicate whether a predetermined number of edges is present in the set of samples, and a phase detector configured to determine a skew condition and a direction of the skew condition of the set of samples based on the indication of the dynamic phase decision control circuit. The phase detector is configured to produce a set of skew detection signals based on at least one skew condition determination. The phase-locked loop further includes a loop filter configured to filter the set of skew detection signals. The loop filter is also configured to produce a set of phase adjustment signals based on the set of skew detection signals. The sample selector is configured to select a set of samples from the oversampled portion of the data signal, based on the set of phase adjustment signals.

Abstract: A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.

Abstract: An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an I/O pad of an electronic circuit, the ESD protection circuit comprising an electrostatic discharge (ESD) circuit that, when activated, discharges an ESD from a first voltage bus to a second voltage bus. The second voltage bus is at a lower electrical potential than the first voltage bus. An ESD discharge control circuit in electrical connection with the ESD discharge circuit that controls the activation of the ESD discharge circuit and including an NMOS transistor and an electrical node. The NMOS transistor regulating a rate of voltage decay of the electrical node from a predetermined high voltage level to a lower voltage level, the regulation of the rate of voltage decay of the electrical node is non-linear. The activation of the ESD discharge circuit determined by the rate of voltage decay of the electrical node.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: An extended range voltage controller oscillator (VCO) circuit for use in a phase-locked loop (PLL) circuit is provided. The VCO circuit includes two additional pairs of varactors which are used to extend the range of the VCO circuit around its center frequency.

Abstract: A control circuit includes a phase frequency detector that receives a reference phase ?REF (signal) as an input and a feedback phase ?FBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase ?FBK (signal). An auxiliary feedback loop receives error phase ?E (signal) from each of the reference phase ?REF (signal) and the feedback phase ?FBK (signal). The auxiliary feedback loop provides an adjustment signal to the control circuit to correct for static phase offset.

Abstract: An auto-adaptive digital phase locked loop (DPLL) includes a phase detector comprising an edge detector having an input that receives an input clock, and an output that outputs a reference event generated from a reference edge of the input clock. The DPLL also includes a programmable first counter that counts down at the generated clock rate, the first counter having a first input that is programmed with an integer value M, a second input that receives the generated clock, and an output that outputs a counter state based on the generated clock and the integer value M. A first register has a first input that receives the reference event, a second input that receives the counter state, and an output that outputs a sample value N(t), wherein the register stores the counter state as the sampled value N(t) that represents a code for a phase between the reference event and the counter state.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract: A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also includes first and second bias switching NMOS. The first bias switching NMOS is coupled between the source of the third NMOS and ground, and the gate of the first bias switching NMOS is coupled to the output of the first logic gate. The second bias switching NMOS is electrically coupled between the source of the fourth NMOS and ground, and the gate of the second bias switching NMOS is coupled to the output of the second logic gate.

Abstract: A complementary output driver includes a driver input that receives an input signal which alternates between a first state and a second state. A first inverter has a first input and a first output. The first input is coupled to the driver input and the first output generates a complementary output signal that is the complement of a present state of the input signal. A second inverter has a second input and a second output. The second input is coupled to the first output of the first inverter and the second output generates an output signal that is the complement of the present state of the first output. A push-pull network has a push-pull input and a push-pull output. The push-pull input is coupled to the driver input and the push-pull output is coupled to the second output.