Abstract: A high voltage isolation circuit for CMOS networks includes a N-channel MOS pass transistor for isolating a high voltage node from a low voltage node so as to prevent CMOS latch-up. There is provided a substrate of N-conductivity type and a P-conductivity region diffused in the substrate to form a PN junction. A supply potential is applied to the substrate. The pass transistor has a conduction path and a control electrode in which one end of the conduction path defines a first node for receiving thereat a first voltage, and the other end of the conduction path defines a second node for receiving thereat a second voltage. The first node is connected to the P-conductivity region. During a first mode of operation, the pass transistor is rendered more conductive so that the first node is coupled to the second node so that the second voltage follows the first voltage.