Abstract: An encoding system manipulates L m-bit data symbols or sequences in accordance with a “restricted-symbol” code to produce code words that include error correction code (ECC) redundancy information and also meet modulation requirements, such as run length. The system combines the data and associated redundancy information of a code word D of the underlying code and one or more predetermined symbols or sequences that are appended to the data code word with the corresponding symbols or bit sequences of a selected code word F, to produce a transmission code word C that consists of symbols or sequences that meet the modulation requirements. Thereafter, the system corrects any errors in the retrieved or received code word C using the included redundancy information and the L m-bit data symbols or sequences are then recovered by removing therefrom the contributions of the code word F.
Abstract: A system with predefined primary and secondary routes sets up corresponding virtual circuits over both routes. A destination node maintains primary and secondary sets of routing tables that contain, respectively, routing information over each of the rings for every virtual circuit. A destination node disables the appropriate entries in the routing tables for the non-selected route, such that the node ultimately discards the traffic received over that route. To switch a virtual path, and thus all of the virtual circuits included therein, from the selected route to the nonselected route, the destination node disables and enables the appropriate entries in the primary and the secondary routing tables, to switch from using the set-up virtual circuits on the selected route to using the set-up virtual circuits on the non-selected route. To detect an event that triggers protection switching, such as path failure, the system uses “Continuity OAM cells” to provide path status information to the nodes.
March 25, 1999
Date of Patent:
March 25, 2003
Dan Cedrone, Walter Dray, Ed Klein, James Regan, Bappa Sinha, Ming-Teh Ma, Jeffrey Weiss
Abstract: A system for producing a quotient B/A, where A and B are elements of GF(22M), 2M+1 is prime and 2 is a primitive element of GF(2M+1), first determines A−1 and then multiplies B by A−1. The system uses a (2M+1)-bit representation for A and produces, directly from A, an element C=A2M+1, where C also is an element of GF(22M) which is a subfield of GF(2M). The system produces M+1 bits to represent C by performing bit manipulations that are equivalent to permuting the (2M+1)-bits to produce A2M and multiplying the permuted bits by A. The bit manipulations are: c0=&Sgr;aiai; c1=&Sgr;aiai+1 . . . cM=&Sgr;aiai+M where the aj's and cj's are the coefficients of A and C, respectively. The system retrieves C−1 from a (2M−1)-element lookup table and multiplies C−1=A−2M+1 by A2M to produce A−1.
Abstract: The encoder/decoder system uses encoder hardware to encode data symbols and form a data code word. To decode, the system uses the same encoder hardware to determine a residue r(x), i.e. ##EQU1## where C.sub.r (x) is the retrieved code word and g(x) is the generator polynomial. If the residue is all zeros, the ECC code word is error-free and the system need not calculate the error syndrome. If the residue is non-zero, the encoder hardware is used, with various switches in different settings, to include certain multipliers in and exclude other multipliers from the further decoding operations of encoding the residue symbols to produce partial error syndromes that are the coefficients of the error syndrome polynomial.
Abstract: A two-level error correction encoder encodes m-bit data symbols in a first level of encoding in accordance with a distance d ECC over GF(2.sup.m+i) to produce (m+i)-bit ECC redundancy symbols and, during a second level of encoding, both modifies the set of ECC redundancy symbols, as necessary, to set i selected bits in each symbol in a predetermined truncation pattern and appends to the set of ECC symbols one or more pseudo redundancy symbols. The encoder includes d-1 Galois Field multipliers, and d-1 associated redundancy-symbol registers and an ECC symbol modifier lookup table that has stored therein information that the encoder uses during the second level of encoding. After the first level of encoding, the d-1 registers contain the (m+i)-bit ECC redundancy symbols.
September 30, 1997
Date of Patent:
March 30, 1999
Shih Mo, Stanley Chang, Lih-Jyh Weng, Ba-Zhong Shen
Abstract: An error correction system includes an encoder that uses a modified Reed-Solomon code to encode m-bit data symbols over GF(2.sup.m+i) and form a preliminary code with d-1 (m+i)-bit ECC symbols. The encoder then modifies the ECC symbols by combining the preliminary code word with a combination of one or more modifying code words to produce modified ECC symbols that have i bits set in a pre-selected pattern. This combination also results in "R" pseudo redundancy symbols that include the i-bit pattern being appended to the modified ECC symbols. The encoder truncates the i-bit pattern from each of the ECC symbols and the pseudo-redundancy symbols, to produce a data code word that has symbols that are elements of GF(2.sup.m).
Abstract: A multiple-solid-burst error correcting system determines the number and locations of "solid burst" errors in a high-rate Reed Solomon or BCH code by determining the greatest common divisor of the error locator polynomial .sigma.(x), which has roots .alpha..sup.-i.sbsp.k that correspond to error locations i.sub.k, and a mapping error locator polynomial .sigma.(.alpha.*x) that maps the error locations , i.sub.k, to locations i.sub.k+1. The roots that are common to both polynomials, that is, the roots that are included in the greatest common divisor, d(x), correspond to adjacent error locations that are contained in the solid bursts. The roots of the non-common factors, p.sub.1 (x), of the error locator polynomial correspond to the first locations of the respective solid bursts and the roots of the non-common factors p.sub.2 (x) of the mapping error locator polynomial correspond to one location beyond the end locations of the solid bursts.
Abstract: A burst error counting system determines for each sector-long error pattern a unique, minimum number of burst errors by (i) specifying, based on the statistical operation of the system, a maximum burst length, L; (ii) determining the location in the error pattern of a first erroneous bit, b.sub.FIRST ; (iii) associating the next L-1 bits with b.sub.FIRST ; (iv) incrementing a burst counter; (v) searching for a next b.sub.FIRST in the remaining bits of the error pattern; and (vi) repeating iii-v. The system may also store the position, that is, bit count, of these b.sub.FIRST 's. Each time the burst error count is incremented, the system compares the count to a predetermined burst error threshold, which is equal to or less than the maximum number of burst errors that can be expected in a sector that is not corrupted to a point at which error correction may produce an incorrect result.
Abstract: An encoding system uses a modified 8/9 rate modulation code to encode 8-bit data symbols into 9-bit cells in a conventional manner in accordance with the modified code and 9-bit ECC symbols into 10-bit cells by (i) encoding 8 bits of the symbol into a 9-bit cell in accordance with the modified code, and (ii) inserting into the 9-bit cell the remaining, that is, the non-encoded, bit of the ECC symbol. The system reproduces the 8-bit data symbols by decoding the 9-bit cells in a conventional manner in accordance with the modified code, and the 9-bit ECC symbols by (i) removing from the associated 10-bit cell the bit inserted during encoding, (ii) decoding the remaining 9 bits to reproduce 8 bits of the symbol, and (iii) inserting into the 8 bits the bit that was earlier removed. In an exemplary embodiment, the 8 least significant bits of the ECC symbol are encoded using the modified 8/9 rate code. The 9 bits produced by the code are used essentially as the first "c" bits and last "10-c" bits of a 10-bit cell.