Patents Represented by Attorney, Agent or Law Firm Patrick D. Benedicto
  • Patent number: 6201377
    Abstract: A match-insensitive low current bias circuit uses a transistor arrangement which takes advantage of the transistors' collector current degeneration, current gain through emitter sizing, and voltage gain to minimize any errors caused by stage mismatches created during production. The bias circuit of the present invention is particularly suited to integrated circuit applications where a low biasing current is required.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: March 13, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Don R. Sauer