Abstract: Digital signals are processed by a first accumulator to generate most significant bits which represent the signal to be converted but with truncation noise. The error signals from the first accumulator are processed by a second accumulator to generate a second set of most significant bits which are used to remove the truncation noise. The most significant bits from the second accumulator are converted to analog form, differentiated and then combined with the most significant bits from the first accumulator after being converted from digital to analog form. The combined signal is then amplified and filtered.

Abstract: Fair and fast service to a plurality of channels served by packet switches at nodes interconnected through a common carrier facility is achieved by controlling the quantity of data sent from any one channel to another. When data arrives at a node from a channel, the channel address is entered in line in the first of two channel address queues and the data is entered in a separate data queue. Each channel address is read from the first queue, a predetermined number of data bytes is read from the corresponding data queue and sent in a frame to a distant node. Thereafter, the channel address is entered at the end of the second, lower priority queue. The frame may have data bytes from other first queue channels but the frame length is limited either by a predetermined number of bytes or when no more channel addresses remain in the first queue. When no channel addresses remain in the first queue, a new frame is started by reading a channel address from the lower priority second queue.

Abstract: A stream of binary bits is converted into blocks of eight parallel bits. A first group of five of the eight bits addresses a memory device which has thirty-two code words each having four numbers representing the coordinates of signal points in four-dimensional space. The remaining three of the eight bits are expanded to four bits by a convolutional encoder having three bits of memory. These four bits are then used to multiply the four numbers of a code word read out from the memory device. This method permits a block of eight binary bits to be coded into any one of five hundred and twelve four-dimensional code words.

Abstract: A distortion simulating pilot is injected at the input of an amplifier which uses feed forward distortion correction. The magnitude of the pilot signal in the amplifier output is used to control a decreasing step size circuit algorithm for adjusting the gain and phase of the feed forward distortion signal to eliminate substantially the pilot signal and the distortion introduced by the amplifier.

Abstract: A methodology for decomposing a three-wire equivalent circuit into a cascade arrangement of a two-wire transmission line and a three-port terminating network is disclosed. Decomposition synthesis is accomplished by iteratively separating the equivalent circuit into the two component parts according to a predetermined algorithm and then comparing the derived three-port network to each network within a class requiring identification, thereby effecting an identification whenever a match occurs. Upon a matched condition, the resistance of the transmission line corresponds to the distance to the terminating network and may be used for fault diagnosis purposes.

Abstract: A programmable digital controller has an address matrix memory (20) and an instruction matrix memory (10). The address memory stores address words each having the address of the first sample and the number of samples in a unique group of samples. Unique groups of samples are sequentially stored in an instruction matrix memory. Each column of the instruction memory has data bits for regenerating an instruction set for controlling any one of many apparatus or processes. Each row of the instruction memory has a sample from each instruction set. In response to an enabling signal, the words from the address memory are sequentially read, interpreted, and the samples from the instruction memory caused to be read and for reconstructing the instruction set.

Abstract: A driver circuit turns an LED `on` and `off` in response to input logic `one` and `zero` data signals. A current regulator 11 is series coupled with the LED and serves to maintain a constant current to the LED over time, temperature, and supply voltage variations. During turn-off, this current is shunted away from the LED by a low impedance emitter follower (Q3), operated in the active non-saturated region, and a small reverse bias potential is momentarily applied to the LED which quickly sweeps out the charge stored in the LED junction. At the end of the `off` cycle there is a forward prebias potential across the LED. During turn-on, the current shunt is reverse biased and a current peaking circuit (14) provides a momentary additional current through the LED. This instantaneous forward current peaking and the forward prebias both serve to substantially reduce the turn-on delay and rise time of the optical drive signal.

Abstract: A fractionally spaced adaptive equalizer is disclosed wherein the coefficients (C.sub.-2 to C.sub.+2) are updated synchronously by an integral -T error circuit (40) and alternately by a fractional =T error circuit (48). This arrangement features a single unique minimum for the adaptive structure thereby preventing the coefficient drift to very large values so coefficient tap leakage is not required to minimize coefficient values. The adaptive characteristic is well suited for linearly dispersive channels, such as exhibited during terrestrial radio transmission during tropospheric multipath propagation. The inventive principles are broadly applicable to any of the well known algorithms for adapting digital filters. A configuration of fractionally spaced equalizers (70.sub.1 -70.sub.4) provides the benefits of Nyquist-rate coefficient updating for a dual rail quadrature amplitude modulated (QAM) signal application.

Abstract: A split-barrel connector terminal is presented wherein a wire connected to the terminal is released as a new wire is being connected. This feature is provided by aperture (13) located a predetermined distance from the wire receiving end of slot (12). When insertion tool (51) forces wire (61) into slot (12), wire (52) is pushed into aperture (13) terminating its mechanical and electrical connection to terminal (11). Terminal (11) has locking shoulders (17) and (18) which permit insertion of the terminal into insulation sheet (32) but prevent removal of the terminal. Sheet (32) and sheet (33) are molded pieces which fit together to provide insulating housing structures for terminal (11). Slot (43) in the housing secures the wires connected to terminals (11) and provides a strain relief function. This arrangement reduces the number of parts making an otherwise complex assembly easily and economically manufacturable.