Abstract: A light emitting diode projection apparatus and method is provided for irradiating a subject with ultraviolet radiation, comprising a plurality of light emitting diodes configured to emit ultraviolet radiation and arranged in a matrix, and a power modulation control unit in communication with the diodes. The power modulation control unit is configured to energize and cause the diodes to emit light and thereby irradiate the subject with ultraviolet radiation sufficient to cause material physical change in the subject. In one embodiment of the invention, the material physical change is skin tanning. The amount, intensity, duration and type of UVR projected by the plurality of UV LED's may be varied by the power modulation control unit responsive to information input into the power modulation control unit.

Abstract: A method and structure for electrically and mechanically interconnecting an array of printed circuit board contacts to an array of module contacts with a plurality of deformable resilient electrical conductors with two ends. Each of the conductor ends are electrically connected to one of the contact arrays. A portion of the conductor may deform longitudinally and laterally responsive to movement of the printed circuit board relative to the module responsive to heating and cooling cycles and mechanical vibrations, while maintaining the electrical connection of the contact arrays. An interposer with apertures extending through the interposer carries the conductors in the apertures and is used to align the conductors with the contacts. A method for excluding a rigid adhesive means from a portion of the resilient conductor is also taught.

Abstract: A method of forming a printed circuit board comprising a plurality of conductive bumps with substantially coplanar upper surfaces. The method comprises the steps of applying a metal layer onto a dielectric substrate; applying a first photoresist onto said substrate and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The present invention is also provides a method for preparing a reinforced panel.

Abstract: The present invention provides a printed circuit board and a method for the production of a printed circuit board having fine-line circuitry and greater aspect ratio on a subcomposite with plated through holes. A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

Abstract: A method of capturing data having the steps of writing on a form with a pen to leave an image on the form, scanning the written image as the written image is being written, and storing the scanned written image in a specific data field. A method of capturing an input, including written information, sounds and images includes the steps of specifying a data field by touching a pen tip to a data-field-specific area on a form; supplying the input; electronically capturing the input and associating the input with the specified data field. An information capturing system, includes a pen, the pen including a writing tip and a position transducer to determine the position of the writing tip relative to a form.

Abstract: A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.

Abstract: A photolithography imaging system and method that performs the tasks of mask alignment, panel recognition, establishing position offsets and adjusting mask rotation for accurate overlay imaging of the mask onto the panel, and correctly adjusting image magnification or reduction to properly size each stepped image to the panel distortion. This invention applies more directly to substrate panels whose dimensional stability is found difficult to control, repeatedly. More specifically, it applies to panels whose X axis distortion factor varies greatly from its Y axis distortion factor and the average adjustment of the image magnification or reduction does not satisfy tight registration requirements. What is new is that the calculation of the magnification or reduction adjustment is based on the mask image dimensions.

Abstract: CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be altered by extrusion or other physical processes, such as liquid crystalline polyesters, that modifies the CTE of at least one component of the package and thereby reduces CTE differentials. The material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required.

Abstract: A method is provided for utilizing a memory system which allows for the fast and efficient writing and reading of objects to and from diverse memory chips. A computer system and memory system complex according to method is also provided. The invention defines objects in terms of “shapes.” The shape of an object is defined by two parameters: “Width” and “Height.” Memory system memory chips may comprise sets of different kinds of memory modules which vary in terms of access speed, latency and memory width, such as for example DRAM or SRAM memory modules. The Height of an object denotes the number of consecutive address locations at which the object is stored on a memory module. The Width of an object denotes the number of memory modules at which the object is stored. An advantage of the invention is that objects are defined in terms of “sub-objects” optimized for the memory system memory modules.

Abstract: A sharpening tool for the sharpening of single and double-beveled edge knives, broadhead arrows and related implements. The sharpener comprises a body with a handle, a handguard, and recesses for detachably mounting pairs of rectilinear sharpening and non-sharpening elements. The recesses are adapted so that a pair of mounted elements form a “V” shaped cutting angle of a constant degree. The pair of elements comprises two sharpening elements for double-beveled edge blades, and one sharpening element and one non-sharpening rest element for single-beveled edge blades. The “V-shaped” cutting angle formed by the mountd elements is imparted to a knife edge being sharpened, and accordingly the degree of angle is defined as the optimal blade edge cutting angle. The recesses are further adapted so that the overlapping sharpening and non-sharpening elements do not contact each other, preventing the elements from vibrating against each other and thereby extending the useful life of the elements.

Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate.

Abstract: The present invention provides a method and structure for connecting a module to a printed circuit board, wherein a substantially rigid interposer having resilient conductors is disposed between a module and a printed circuit board. A clamping means urges the module and printed circuit board toward each other with compressive force upon an interposer positioned therebetween, preferably causing the module and printed circuit board to deform and thereby align their electrical contacts with the surfaces of the interposer. The interposer further comprises a plurality of apertures, each aperture further having a deformable resilient conductor means for connecting a module contact to a PCB contact. The conductor is deformable in shear, which may travel and, therefore, makeup the CTE dimensional mismatch between the module and the PCB. The conductors are detachable, electrically connecting the module and PCB contacts without the requirement of solder or other permanent means.

Abstract: A content addressable memory (CAM) structure and method that provides a redundant scheme for an ASIC. The scheme comprises a CAM comparative means for bypassing normal encoders, including a fuse structure having a fuse address list and a “CAM row compare” structure. Redundancy is provided in “CAM Search Read” and “CAM Search Read and RAM Read” operations. Normal CAM memory address rows and redundant replacement CAM memory address rows are provided for bank addresses. A miss logic is provided for detecting a bank address miss and generating a responsive miss signal, and an “address out” logic is also provided to pass only one of a generated normal CAM memory address row, redundant replacement address row or miss signal in a bank. The method and structure can support different address sizes and different cache sizes.

Abstract: A hand tool comprising a first handle member with integral jaw, a second handle member, and a third jaw member, all three members pivotally connected by a single common pivot pin. All three members are also cooperatively connected by a force multiplying mechanism, wherein an operative force applied to the handles is multiplied and applied to a work piece by the jaws. One embodiment of the invention features a “U”-shaped handle with two common pivot pin connection points, providing structural strength and handling stability. Other embodiments also comprise power assist devices to provide electrical and pneumatic work piece manipulation forces.

Abstract: An electronic circuit package includes a metal carrier, a first dielectric layer of an epoxy glass material, a first electrically conductive circuit layer, a second dielectric layer, a second electrically conductive circuit layer and an electrical interconnection between the first and second electrically conductive circuit layers. The electronic circuit package affords improved electrical breakdown resistance.

Abstract: A printed circuit board comprising a plurality of conductive bumps having substantially coplanar upper surfaces is provided. The circuit board is formed by providing: a substantially planar metallic layer having a first thickness on at least one surface of the dielectric; applying a first photoresist on the metal layer; imaging the first photoresist to define a pattern of conductive bumps; etching the exposed portions of the metal layer to a second thickness to form the conductive bumps; removing the first photoresist; applying a second photoresist to the metal layer; imaging the second photoresist to define a pattern of circuitry; etching the exposed portions of the metal layer to provide the electrical circuitry; and removing the second photoresist. The present invention also provides a method for preparing printed circuit boards wherein two conductive layers that are disposed on opposing sides of a dielectric layer are inter-connected by at least one of the substantially coplanar conductive bumps.

Abstract: A method of generating artifact-free threshold matrices for digital printing devices is provided. The method includes, for example, the steps of establishing a threshold matrix by examining at least one color level for artifacts and removing the color level from the threshold matrix if it has artifacts. The method further includes the steps of examining a range of color levels for artifacts and removing the color levels from the threshold matrix which have artifacts and evenly distributing the remaining color levels over a range of color levels from a first color level to a last color. The examination of color levels for artifacts may be implemented manually or through an automated computer controlled process. The automated process includes digitally acquiring the color level and performing a Fourier transform on the color level to determine its spectral components. The spectral components are analyzed to determine the presence or absence of artifacts.

Abstract: CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be altered by extrusion or other physical processes, such as liquid crystalline polyesters, that modifies the thermal expansion of at least one component of the package and thereby reduces CTE differentials. The material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required.

Abstract: A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive controller/coprocessor. The computer system has a central processing unit (CPU) with at least one bus associated therewith, with the bus having at least one bus line. The cartridge comprises a readable memory, a memory control circuit, a lock control circuit, and a connector all in circuit communication with each other. The connector allows the memory, the memory control circuit, and the lock control circuit to be pluggably connected in circuit communication with the CPU. The memory control circuit scrambles some of the bus lines, thereby scrambling the data in the memory on reset, and unscrambles the bus lines responsive to inputs from the lock control circuit.

Abstract: A system and method for the fault simulation testing of circuits by using a behavioral model is provided. The behavioral model includes a fault bus, decoder, and input and output ports. The decoder decodes mapping fault values, which are applied to the fault bus, to either a no-fault or to a specific fault which is internally encoded into the behavioral model. Accordingly, a single behavioral model can be used to dynamically model a fault-free circuit or machine and one or more faulty circuits or machines based on the mapping fault data applied to each model's fault bus. A fault simulation tool applies test simulation data having mapping fault and test parameter data to at least two identically coded behavioral models (i.e., a fault-free model and a faulty model, as defined by the applied mapping fault data). Output data are generated by each behavioral model and recorded by the fault simulation tool.