Abstract: A circuit board is provided which has contacts on the surface arrayed to engage contact pads on a chip carrier bounded by a grid. A plurality of primary through holes are provided in the circuit board location within the grid and electrically connected to chip contact pads thereabove. A plurality of secondary through holes are provided which are located outside the grid and electrically connected to the inside of the chip contact pads. The spacing of the contacts on top of the board is less than the spacing of the contacts on the bottom.

Abstract: A low profile riser card assembly for a computer system is provided by incorporating two uniaxial back to back peripheral connectors. The peripheral card connectors extend outwardly along a single axis from opposing sides of a riser card. The riser card is attached to a riser card connector mounted on the circuit board and is held in a perpendicular to the axis and in an upright position with respect to the circuit board. In the assembly of the present single invention, the uniaxial back to back peripheral card connectors are retained on the riser card in a parallel orientation with respect to the riser card connector to produce a low profile computer assembly.

Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate.

Abstract: A computer system having suspend and resume capabilities that uses the hard drive to extend the amount of nonvolatile memory (NVRAM) in the system. As the system is powered down, the system processor saves to the hard drive system parameters such as: resource allocation data determined pursuant to the Plug & Play specification, total power on hours for the system, the number of power on cycles for the system, error codes, and the dates the errors occurred. The saving to hard drive begins responsive to circuitry monitoring the primary (AC input) portion of the power supply indicating that the power supply input is out of tolerance, as would occur when the user actuates the power switch to turn the system off or during a blackout. During the period of reliable processing time remaining, the above system parameters are written to the hard file. The system parameters are also saved to the hard file during the controlled power off that occurs as the system state is suspended.

Abstract: A computer system having interrupts synchronized to data storage by having an interrupt data signal (interrupt packet) follow the path of the data to an interrupt receiver, which interrupts the processor to execute an interrupt service routine. Rather than having a dedicated interrupt line from a peripheral device to a processor, the peripheral device sends the interrupt across a bus from the peripheral to the processing unit via an interrupt receiver.