Abstract: A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage.