Abstract: A low-temperature semiconductor device test apparatus that includes a device tester having a purge box mounted thereon, a low-temperature handler system, and a load board having a IC test socket. The purge box is located between the load board and a support plate of the device tester, and between groups of compressible test pins used to pass test signals to the test socket through conductive traces formed in the load board. The purge box includes rigid outer walls defining a chamber that is located opposite to the test sockets. During low-temperature testing, dry air is pumped into the chamber through conduits formed in the walls of the purge box to prevent the condensation of moisture on conductors formed on the load board and exposed in the chamber. In addition, the purge box resists bending of the load board when semiconductor devices are pressed against the test sockets.
Abstract: A method for testing packaged integrated circuits (ICs) having bent or broken leads. A lower portion of each lead is cut to leave a stub located close to the package body of the damaged IC. The damaged IC is then mounted onto a probe card having upward-facing probes that contact the lead stubs. Test signals are then transmitted between an IC tester and the damaged IC through the probe card.