Patents Represented by Attorney Patterson & Sheridan
  • Patent number: 8307165
    Abstract: One embodiment of the invention sets forth a mechanism for increasing the number of read commands or write commands transmitted to an activated bank page in the DRAM. Read requests and dirty notifications are organized in a read request sorter or a dirty notification sorter, respectively, and each sorter includes multiple sets with entries that may be associated with different bank pages in the DRAM. Read requests and dirty notifications are stored in read request lists and dirty notification lists, where each list is associated with a specific bank page. When a bank page is activated to process read requests, read commands associated with read requests stored in a particular read request list are transmitted to the bank page. When a bank page is activated to process dirty notifications, write commands associated with dirty notifications stored in a particular dirty notification list are transmitted to the bank page.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: November 6, 2012
    Assignee: Nvidia Corporation
    Inventors: Shane Keil, John H. Edmondson, Sean J. Treichler
  • Patent number: 8300350
    Abstract: According to one embodiment, a magnetic disk drive comprises a write count memory, a read offset setting module and a controller. The write count memory stores a write count for each track or for each zone on a disk. The read offset setting module sets, in accordance with a write count for an adjacent track to a target track or for a zone to which the adjacent track belongs, an offset from a predetermined position on the target track in a read position in which a head is to be positioned when the head is positioned on the target track for data read. The write count is stored in the write count memory. The controller positions the head in a position shifted from the predetermined position by the set offset.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Kawabe
  • Patent number: 8297607
    Abstract: According to one embodiment, a sheet processing apparatus includes a reinforce roller to further reinforce the fold of a sheet which has been folded by a fold roller pair, a support portion to move the reinforce roller in a direction perpendicular to a sheet conveying direction, a sensor to sense a position of the support portion, a distance sensing portion to sense a distance to a first position and a distance to a second position from a stop position of the support portion, when the sensor senses an abnormal stop of the support portion, and a control unit to compare the distance to the first position and the distance to the second position sensed by the distance sensing portion and to control the support portion to move in a direction where a moving distance is shorter.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 30, 2012
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Isao Yahata, Hiroyuki Taguchi
  • Patent number: 8298879
    Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: October 30, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8297591
    Abstract: Embodiments disclosed herein generally relate to methods for sealing a processing chamber with a slit valve door. The door initially raises from a position below the opening for the processing chamber to a raised position. The door then expands until an O-ring that is on the door just touches the sealing surface. Then, the door expands again to compress the O-ring against the sealing surface. The door expands by flowing a gas into the interior volume of the door. By controlling the pressure buildup within the door, the speed with which the door expands is controlled to ensure that the door gently contacts the sealing surface and then compresses against the sealing surface. Thus, the door may be prevented from contacting the sealing surface with too great a force that may jolt or shake the processing chamber and produce undesired particles that may contaminate the process.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: October 30, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Takayuki Matsumoto, Shinichi Kurita
  • Patent number: 8301786
    Abstract: Network devices, computer-readable media, and other embodiments associated with packet inspection are described. Packet inspection may be performed on data packets associated with a session, where a session can include multiple data channels and associated control channels that have been bound together. A session may be associated with an identity. Various policies may be associated with that identity. As packet inspection occurs, it can be determined whether policies are being violated on a per identity basis. If a policy is being violated, then an action may be selectively performed. The action performed may affect a single channel in the session or may affect the whole session. Different identities may have different policies. Example actions include dropping a session, throttling a session, monitoring a session, controlling the number of channels associated with a session, dropping a channel, throttling a channel, monitoring a channel, and other actions.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: October 30, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Praveenkumar Reguraman, Rajasekhar Manam, Sridar Kandaswamy, Abhijit V. Warkhedi
  • Patent number: 8301871
    Abstract: A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between the branch instruction and the target instruction. The method further includes issuing the one or more interceding instructions and the target instruction and determining if the branch instruction follows the first path or the second path. Upon determining that the branch instruction follows the first path, the one or more interceding instructions between the branch instruction and the target instruction are invalidated.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventor: David A. Luick
  • Patent number: 8300365
    Abstract: An electronic substrate includes: a flexible printed circuit comprising a head connecting portion being provided with a first terminal to be electrically connected to a magnetic head, and a board connecting portion being provided with a second terminal to be electrically connected to a main printed board; a first reinforcing member provided on the head connecting portion of the flexible printed circuit, the first reinforcing member reinforcing the head connecting portion; and a second reinforcing member provided on the board connecting portion of the flexible printed circuit, the second reinforcing member reinforcing the board connecting portion, wherein the second reinforcing member includes a additional enhancement portion formed with a sterically enhanced shape.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Awaga, Kengo Saruta, Takao Ohmi
  • Patent number: 8300271
    Abstract: An image process system applies a specific process to image data inputted via an input device and outputs the image data, to which the specific process has been applied, to an output device. The system includes: an input information acquisition portion that acquires information about the input device through which the image data is inputted; an output information acquisition portion that acquires information about the output device to which the image data inputted via the input device is to be outputted; a process execution portion that executes the specific process to the image data inputted via the input device on the basis of the information acquired by the input information acquisition portion and the output information acquisition portion; and a data output portion that outputs the image data, to which the specific process has been applied in the process execution portion, to the output device.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: October 30, 2012
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventor: Takahiro Hagiwara
  • Patent number: 8299523
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura
  • Patent number: 8301980
    Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: October 30, 2012
    Assignee: NVIDIA Corporation
    Inventors: Fred Gruner, Shane Keil, John S. Montrym
  • Patent number: 8300523
    Abstract: In one embodiment a method is provided for forwarding traffic through a standby device in the event of an uplink connection failure. The method generally includes forwarding traffic received on a first downlink connection with a dual-homed device to an uplink connection with a network core, detecting a failure on the uplink connection with the network core, and in response to detecting the failure, notifying a standby device of the failure and sending a message to the dual-homed device to trigger the dual-homed device to begin forwarding traffic to the network core via a second downlink connection between the standby device and the dual-homed device.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: October 30, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Samer M. Salam, Ali Sajassi
  • Patent number: 8300147
    Abstract: A system and method for characterizing the relative offset in time between audio and video signals and enables the receiver of the audio and video signals to resynchronize the audio and video signals. Signal characterization data is dynamically captured and encoded into frames of video and audio data that is output by a television origination facility. The signal characterization data is extracted by the receiver and signal characterization data is captured for the received frames. The extracted signal characterization data is compared with the captured signal characterization data to compute the relative offset in time between the video and one or more audio signals for a frame. The receiver may then resynchronize the video and audio signals using the computed relative offset.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 30, 2012
    Assignee: Disney Enterprises, Inc.
    Inventors: Michael J. Strein, Efthimis Stefanidis, James L. Jackson
  • Patent number: 8297417
    Abstract: A front bicycle suspension assembly having an inertia valve is described. The front bicycle suspension assembly may include at least upper and lower telescoping tubes and include a damping tube containing an inertia valve. The inertia valve may include an inertia mass movable along the outer surface of a valve shaft as the inertia valve moves between first and second positions.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: October 30, 2012
    Assignee: Fox Factory, Inc.
    Inventor: Robert C. Fox
  • Patent number: 8301063
    Abstract: A toner cartridge includes a toner receptacle that houses toner, a plurality of stirring members housed in the toner receptacle, a plurality of gears meshing with each other on outside of the toner receptacle, and a phase display section. The stirring members are arranged next to each other in the toner receptacle and rotate to stir the toner. Each of the stirring members has a scraper that scrapes off the toner adhering to an inner surface of the toner receptacle. The gears rotate to rotate the stirring members in an interlocked manner with each other. The phase display section shows a meshing position of the gears so that the gears mesh with each other at a position where a phase difference along a rotating direction of the stirring members occurs between the scrapers of the stirring members that are next to each other.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: October 30, 2012
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventor: Yoshiaki Tanaka
  • Patent number: 8299466
    Abstract: Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: October 30, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Gaku Furuta, Soo Young Choi, Omori Kenji
  • Patent number: 8299548
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include simultaneously forming a first field insulating film and at least one second field insulating film on a front face side of a semiconductor layer. The at least one second field insulating film is separated from the first field insulating film and thinner than the first field insulating film. The method can include forming a drift region of a first conductivity type in a region of the semiconductor layer including the first field insulating film and the second field insulating film. The method can include forming a drain region of the first conductivity type in the front face of the semiconductor layer on a side of the first field insulating film. In addition, the method can include forming a source region of the first conductivity type in the front face of the semiconductor layer on a side of the second field insulating film.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanako Komatsu, Tsubasa Yamada, Jun Morioka, Koji Kimura
  • Patent number: 8300647
    Abstract: A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: October 30, 2012
    Assignee: NVIDIA Corporation
    Inventors: Ayaz Abdulla, Norman K. Chen, Anand Rajagopalan, Ashutosh K. Jha, Hemamalini Manickavasagam, Sameer Nanda
  • Patent number: 8301647
    Abstract: Embodiments of the invention allow structured data to be transferred between a source application and target applications that process structured data in different formats. For example, structured data may have associated rules which transform the structured data based on some variables. The source application may register variable definitions for each variable in a registry. Each target application may read the registry and register values for the variables. Once values are registered, the source application transfers the structured data to a transformation engine that applies the rules, using the registered values for the variables, to transform the structured data into a format compatible with the target applications. The transformation engine may also determine distinct sets of variable values and transform structured data based on each distinct set. In doing so, the number of transformed data generated is limited to the number of distinct sets, thereby avoiding generating duplicate transformed data.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Eggebraaten, Jeffrey W. Tenner, Shannon E. Wenzel, Eric W. Will
  • Patent number: D670255
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: November 6, 2012
    Assignee: Gainsborough Hardward Industries Limited
    Inventors: Stuart Clark, Harris Lambrou, Troy Nyssen, Lisa Edlund-Tjernberg, Fred Blochlinger