Abstract: A method, apparatus, article of manufacture, and system, the method including, in some embodiments, determining an impedance of a power distribution network of a load for a range of frequencies, and adjusting a functionality of the load based on a relationship between the impedance of the power distribution network for the range of frequencies and the functionality of the load.

Abstract: In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a network interface component, and a management controller. The management controller may be configured to receive information related to a subscription request for a virtual machine, generate configuration information for the network interface component based on the subscription request, and provide the configuration information to the network interface component. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, a memory control device includes a sensor positioned remotely from a memory device, a register to store an offset value, the offset value corresponding to a difference between a temperature reading of the sensor and an estimated actual temperature of the memory device, and a controller to control an operation of the memory device, wherein the controller is configured to read the offset value from the register and control the operation of the memory device in accordance with the offset value. The controller may be configured to dynamically update the offset value during an operation of the memory device. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a boot block stored at a first memory location, a capsule update stored at a second memory location, a startup authenticated code module to ensure the integrity of the boot block upon a restart of the processor-based system, code which is executable by the processor-based system to cause the processor-based system to validate the boot block with the startup authenticated code module upon the restart of the processor-based system, and, if the boot block is successfully validated, to validate the capsule update for the processor-based system with the startup authenticated code module. Other embodiments are disclosed and claimed.

Abstract: An electronic system may include a memory storing processor-executable program code and a processor in communication with the memory and operative in conjunction with the stored program code to determine a number of retired instructions and a number of input/output queue events for a workload and to determine if a performance characteristic is within a desired performance range based at least in part on the number of retired instructions and the number of input/output queue events. If the performance characteristic is within the desired performance range, the processor may be further operative in conjunction with the stored program code to determine an amount of time on die and an amount of time off die for the workload, to determine if a phase shift occurred based on the amount of time on die and the amount of time of die, and, if the phase shift occurred, to determine a new target frequency for a processor to execute the workload.

Abstract: In some embodiments, a stacked package assembly may include a first socket defining an interior cavity, a first semiconductor device coupled to the first socket, a second socket positioned within the interior cavity of the first socket, and a second semiconductor device removably coupled to the second socket within the cavity of the first socket. The second socket may be positioned between the first semiconductor device and the second semiconductor device and provide an electrical connection between the first semiconductor device and the second semiconductor device. Other embodiments are disclosed and claimed.

Abstract: A pulse width modulation driven display such as a spatial light modulator, which updates pixel data between PWM periods of consecutive frames, to avoid tearing artifacts in the perceived display image.

Abstract: In some embodiments, a drive circuit may be coupled to a spatial light modulator, wherein the drive circuit provides a non-linear analog ramp signal to the spatial light modulator. Other embodiments are disclosed and claimed.

Abstract: Embodiments of a method and/or apparatus to provide a binary image are disclosed.

Abstract: Embodiments of an architecture for processing gray-level images is disclosed.

Abstract: Briefly, in accordance with one embodiment, a circuit to encode binary digital signals so as to reduce EMI emissions during signal transmission across a bus or interconnect includes circuitry to apply a pseudo-random pattern of binary digital signals to encode selected binary digital signals so as to reduce the harmonic content of the selected binary digital signals. Briefly, in accordance with another embodiment, a method of encoding binary digital signals so as to reduce EMI emissions during signal transmission across a bus or interconnect includes applying a pseudo-random pattern of binary digital signals to encode selected binary digital signals so as to reduce the harmonic content of the selected binary digital signals.

Abstract: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An execution unit, which executes a first active thread and a second active thread is coupled to the scheduler unit. The multi-threading processor also includes a register file coupled to the execution unit. The register file switches one of the first active thread and the second active threads with a first inactive thread.

Abstract: A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0<n<=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.

Abstract: An apparatus includes a low magnetic-coercivity layer of material (LMC layer) having a majority electron-spin-polarization (M-ESP), an energy-gap coupled with the LMC layer, wherein a flow of spin-polarized electrons having an electron-spin-polarization anti-parallel to the LMC layer are injected via the energy-gap, to change the M-ESP of the LMC layer. A non-magnetic material is in electrical communication with the LMC layer and provides a spin-balanced source of current to the LMC layer, responsive to the injection of spin-polarized electrons into the LMC layer.

Abstract: Several embodiments in accordance with the invention are disclosed. In one particular embodiment, a display screen for a display is discussed.

Abstract: A signaling mechanism associated with errors in a processor are promoted or demoted based on a set of stored values.

Abstract: An LCOS chip may have a pixel divided into an outer subpixel and an inner subpixel. A driver may independently drive the subpixels. The driving technique may be pulse-width modulation. Because of the pixel is divided into subpixels, pulses of short widths that drive an undivided pixel may be replaced with pulses of longer duration. In an alternative embodiment, the pixel is not divided into subpixels. The driving technique may be a combination of pulse width and pulse height modulation. The waveform may replace pulses of short widths with pulses of longer duration and reduced voltage levels.

Abstract: A spatial light modulator is adapted to receive bidirectional drive signals.

Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.

Abstract: A method of electing a bootstrap processor from among a plurality of processor includes creating an atomic access shared location and electing one of said processors as the bootstrap processor.