Patents Represented by Attorney Paul I. Webb, II
  • Patent number: 4786961
    Abstract: An integrated circuit includes a substrate of one conductivity type silicon and an epitaxial layer of the opposite conductivity type silicon on a surface of the substrate. An emitter region of the one conductivity type is in the epitaxial layer and a collector region of the one conductivity type is in the epitaxial layer and extends around but is spaced from the emitter region. A third region of the one conductivity type is in the epitaxial layer and extends partly around and is spaced from the collector region. A highly conductive connector region of the opposite conductivity type extends into the epitaxial layer to a buried region of the opposite conductivity type which is along the junction of the epixtaxial layer and the substrate. The connector region contacts the third region. A thin layer of silicon oxide extends over the epitaxial layer. Separate contacts extend through the epixtaxial layer to the emitter region, collector region and to adjacent portions of the third region and the collector region.
    Type: Grant
    Filed: February 28, 1986
    Date of Patent: November 22, 1988
    Assignee: General Electric Company
    Inventor: Leslie R. Avery