Abstract: An apparatus, method and system are provided for scanning documents, and creating holographic and panoramic images. The apparatus provides two sets of prisms, one set of which is made of electro-optical material. The prisms are arranged in alternating rows to form a sheet. The prism sheet can be laid flat or rolled into a cylinder. A sequencer is used to activate individual electro-optical prisms so that the image is reflected into the sheet. A second prism is used to reflect the image into an image receptor such as a camera. By sequentially activating the electro-optical prisms, successive image portions of an object or objects can be presented to the image receptor. If the image receptor accepts digital input, the sequential images can be post-processed in a microprocessor to create a holographic or panoramic image. Similarly, images of documents can also be scanned and the images received can be digitized for processing, storage and/or transmission.

Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset.

Abstract: A fast start-up circuit for use in integrated circuits where there are internal nodes of reference circuits that need to be charged to a predetermined voltage level at a quicker rate than that delivered by the typical ramping up of supply power. The circuit a current driven approach, which is unique from the voltage driven approaches found in the prior art. The circuit is comprised of a high gain reference circuit and a current generator. The reference circuit is comprised of a bias generator and a high gain amplifier. The invention is characterized by a current generator which is capable of rapidly injecting relatively high levels of current into the reference circuit or sinking relatively high levels of current from the reference circuit or both. The invention is further characterized by a current driven feedback loop which deactivates the current generator once start-up is achieved and the high gain reference circuit approaches the quiescent point.

Abstract: The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programming logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.

Abstract: A transmitter system having an adjustable monolithic frequency stabilization and tuning internal capacitor circuit. The transmitter system has a transmitter for generating and transmitting a transmitter oscillator frequency signal. A data generating chip is coupled to the transmitter. The data generating chip is used for adjusting and controlling the transmitter oscillator frequency signal. A variable capacitor circuit is located internal to the data generating chip and is coupled to a ground pin and one of a plurality of function pins on the data generating chip. The variable capacitor circuit is used for adjusting and setting the centerpoint of the transmitter oscillator frequency signal.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, or as an interface bridge between a Fibre Channel Arbitrated Loop ("FC-AL") interface and the host and memory buses. The function of the multiple use chipset is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an FC-AL bridge interface is to be implemented. Selection of the type of bus bridge (AGP or FC-AL bridge interface) in the multiple use core logic chipset may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a FC-AL bridge interface device connected to the common AGP/ FC-AL bus. FC-AL information may be stored in the computer system main memory using the high speed FC-AL bridge interface.

Abstract: A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on page 0 of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables which are located on page 0 of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in the op-code instruction currently being executed by the microcontroller.

Abstract: An oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator, two independent current generators, a transition detector and a clock inhibitor. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current that is independent of temperature. The oscillator is capable of three modes of operation: fast mode, slow/low power mode and sleep mode, which are controlled by the transition detector in response to external control signals. When the transition detector transitions from one mode to another, it controls the clock inhibitor to block a clock output of the oscillator generator for a predetermined number of clock cycles to allow the clock output to stabilize. The oscillator is implemented on a single, monolithic integrated circuit.

Abstract: A Full-Wave Bridge Rectifier (FWBR) input structure for use in an electrical system is delineated comprising, in combination, a pair of input nodes, and a pair of parasitic BJTs coupled in parallel with the pair of input nodes wherein each parasitic BJT has more than one collector. The input structure also includes an inductor and a capacitor connected in parallel across the pair of input nodes; however, one or more inductors, one or more capacitors, a transformer, or the like could be substituted. Each parasitic BJT also has a base coupled to ground through a resistor, a collector tied directly to ground, and another collector tied to a supply voltage VDD through a resistor. The area associated with each emitter is smaller than the area associated with their respective collector coupled to VDD. This arrangement of the parasitic BJTs assists in minimizing their gain in order to diminish their draw on a downstream power supply.

Abstract: An engine which employs a cam follower mechanism to reduce wear and reduce the size of an assembled engine. The cam follower mechanism utilizes guide rails located to reduce side thrust on the valve stem. The engine employs a high speed quill shaft to synchronize independent cam shafts existing in each of a plurality of interconnected engines. The engine is assembled using a single size fastener to provide a uniform stress gradient within the engine. The engines are interconnected utilizing O-ring seals. The engine provides a piston crown utilizing a connecting rod directly connected to the bottom surface of the piston crown. The piston crown is stabilized along the longitudinal cylinder axis by a rail guide. Connecting rods are provided which require less than one hundred eighty degrees (180.degree.) circumference of a crankshaft pin for support so that a plurality of connecting rods can be associated with a single crankshaft pin.

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation.

Abstract: An error recovery method and apparatus has specific application in a networking arrangement having a plurality of individual processing nodes which communicate via shared memory space. For error recovery, the system uses a reliable error count, the value of which is maintained by all of the nodes. When an error is detected, the error count is incremented, and all of the active nodes are provided with the new error count. Any of the nodes can run the error recovery method, and may gain exclusive access to the network by acquiring an error recovery spinlock. Once the spinlock is acquired, the node holding the spinlock increments the error count and confirms that all active nodes have received the new error count. The spinlock is thereafter released.

Abstract: An administrator station for administering and maintaining a plurality of computer network and/or communications servers. A low profile clam-shell display and keyboard apparatus, as utilized in a portable notebook computer, is used to replace a rack mounted cathode ray tube video monitor, keyboard and cursor control devices, and an electromechanical switcher. An interface apparatus translates the video output, keyboard and mouse signals of a plurality of computer servers to a format that may be communicated to the administrator station either through a physical connection or by means of wireless communications such as infrared, cellular or spread spectrum radio. When not in use, the administrator station may be stored in a low profile rack panel located in a rack cabinet having a plurality of computer servers mounted therein. Alternatively, the administrator station may be moved from one rack cabinet of computer servers to another.

Abstract: A method and apparatus of assuring uniqueness of identification numbers of bus devices connected to a bus. Each bus device has a current identification number. At each of the bus devices, an identification number is received on a bus and the bus is contended for based on the received identification number. If more than one bus device is detected contending for the bus, the current identification number of one of the bus devices is changed. Each of the bus devices compares the received identification number to the current identification number of the bus device. A bus device provides a match indication, including driving a signal, if the comparison produces a match. Each bus device includes a collision detector for detecting if more than one bus device is driving the signal.

Abstract: A telephone system having a telephone network line for connection to an external phone line. The telephone system also includes a computer system and a telephone coupled to the telephone network line, and the telephone is taken off-hook to enter a voice command. A transmitter communicates the voice command from the telephone to the computer system without the telephone seizing the external phone line. A computer interface unit is connected to the computer system to receive the voice transmitted from the telephone and to transmit voice signals transmitted by the computer system to the telephone. A phone interface unit is connected between the telephone and telephone network line, and the phone interface unit is selectable between a first mode and a second mode. The phone interface unit connects the telephone to the telephone network line if it is in the first mode, and isolates the telephone from the telephone network line if it is in the second mode.