Abstract: A method for setting host bus clock frequencies and processor core clock ratios in a multi-processor computer system. The method first determines original host bus frequency settings for each of the installed processors. The host bus is set to clock at the slowest of the frequency settings. Processor core clock ratios are then optimized for the new host bus frequency. The optimization process commences by determining the original processor core clock ratio settings for each processor. These ratio settings are individually optimized via an iterative process wherein the core clock ratios are incrementally increased and multiplied by the new host bus frequency. This process continues until the incremented core clock ratio yields a core clock frequency in excess of the maximum rating for the processor under test. The core clock ratio is then decremented and latched into the processor under test via a hard reset.